476 lines
12 KiB
C
476 lines
12 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors: Dave Airlie <airlied@redhat.com>
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*/
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#include <linux/pci.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_gem.h>
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#include <drm/drm_gem_vram_helper.h>
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#include <drm/drm_managed.h>
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#include "ast_drv.h"
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void ast_set_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index,
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uint8_t mask, uint8_t val)
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{
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u8 tmp;
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ast_io_write8(ast, base, index);
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tmp = (ast_io_read8(ast, base + 1) & mask) | val;
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ast_set_index_reg(ast, base, index, tmp);
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}
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uint8_t ast_get_index_reg(struct ast_private *ast,
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uint32_t base, uint8_t index)
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{
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uint8_t ret;
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ast_io_write8(ast, base, index);
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ret = ast_io_read8(ast, base + 1);
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return ret;
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}
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uint8_t ast_get_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index, uint8_t mask)
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{
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uint8_t ret;
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ast_io_write8(ast, base, index);
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ret = ast_io_read8(ast, base + 1) & mask;
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return ret;
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}
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static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
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{
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struct device_node *np = dev->dev->of_node;
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struct ast_private *ast = to_ast_private(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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uint32_t data, jregd0, jregd1;
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/* Defaults */
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ast->config_mode = ast_use_defaults;
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*scu_rev = 0xffffffff;
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/* Check if we have device-tree properties */
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if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
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scu_rev)) {
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/* We do, disable P2A access */
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ast->config_mode = ast_use_dt;
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drm_info(dev, "Using device-tree for configuration\n");
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return;
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}
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/* Not all families have a P2A bridge */
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if (pdev->device != PCI_CHIP_AST2000)
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return;
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/*
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* The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
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* is disabled. We force using P2A if VGA only mode bit
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* is set D[7]
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*/
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jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
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jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
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if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
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/* Patch AST2500 */
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if (((pdev->revision & 0xF0) == 0x40)
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&& ((jregd0 & AST_VRAM_INIT_STATUS_MASK) == 0))
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ast_patch_ahb_2500(ast);
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/* Double check it's actually working */
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data = ast_read32(ast, 0xf004);
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if ((data != 0xFFFFFFFF) && (data != 0x00)) {
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/* P2A works, grab silicon revision */
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ast->config_mode = ast_use_p2a;
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drm_info(dev, "Using P2A bridge for configuration\n");
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/* Read SCU7c (silicon revision register) */
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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*scu_rev = ast_read32(ast, 0x1207c);
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return;
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}
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}
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/* We have a P2A bridge but it's disabled */
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drm_info(dev, "P2A bridge disabled, using default configuration\n");
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}
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static int ast_detect_chip(struct drm_device *dev, bool *need_post)
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{
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struct ast_private *ast = to_ast_private(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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uint32_t jreg, scu_rev;
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/*
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* If VGA isn't enabled, we need to enable now or subsequent
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* access to the scratch registers will fail. We also inform
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* our caller that it needs to POST the chip
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* (Assumption: VGA not enabled -> need to POST)
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*/
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if (!ast_is_vga_enabled(dev)) {
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ast_enable_vga(dev);
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drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
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*need_post = true;
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} else
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*need_post = false;
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/* Enable extended register access */
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ast_open_key(ast);
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ast_enable_mmio(dev);
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/* Find out whether P2A works or whether to use device-tree */
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ast_detect_config_mode(dev, &scu_rev);
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/* Identify chipset */
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if (pdev->revision >= 0x50) {
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ast->chip = AST2600;
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drm_info(dev, "AST 2600 detected\n");
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} else if (pdev->revision >= 0x40) {
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ast->chip = AST2500;
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drm_info(dev, "AST 2500 detected\n");
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} else if (pdev->revision >= 0x30) {
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ast->chip = AST2400;
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drm_info(dev, "AST 2400 detected\n");
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} else if (pdev->revision >= 0x20) {
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ast->chip = AST2300;
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drm_info(dev, "AST 2300 detected\n");
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} else if (pdev->revision >= 0x10) {
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switch (scu_rev & 0x0300) {
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case 0x0200:
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ast->chip = AST1100;
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drm_info(dev, "AST 1100 detected\n");
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break;
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case 0x0100:
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ast->chip = AST2200;
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drm_info(dev, "AST 2200 detected\n");
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break;
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case 0x0000:
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ast->chip = AST2150;
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drm_info(dev, "AST 2150 detected\n");
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break;
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default:
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ast->chip = AST2100;
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drm_info(dev, "AST 2100 detected\n");
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break;
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}
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ast->vga2_clone = false;
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} else {
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ast->chip = AST2000;
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drm_info(dev, "AST 2000 detected\n");
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}
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/* Check if we support wide screen */
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switch (ast->chip) {
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case AST2000:
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ast->support_wide_screen = false;
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break;
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default:
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
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if (!(jreg & 0x80))
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ast->support_wide_screen = true;
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else if (jreg & 0x01)
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ast->support_wide_screen = true;
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else {
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ast->support_wide_screen = false;
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if (ast->chip == AST2300 &&
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(scu_rev & 0x300) == 0x0) /* ast1300 */
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ast->support_wide_screen = true;
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if (ast->chip == AST2400 &&
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(scu_rev & 0x300) == 0x100) /* ast1400 */
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ast->support_wide_screen = true;
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if (ast->chip == AST2500 &&
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scu_rev == 0x100) /* ast2510 */
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ast->support_wide_screen = true;
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}
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break;
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}
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/* Check 3rd Tx option (digital output afaik) */
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ast->tx_chip_type = AST_TX_NONE;
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/*
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* VGACRA3 Enhanced Color Mode Register, check if DVO is already
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* enabled, in that case, assume we have a SIL164 TMDS transmitter
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*
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* Don't make that assumption if we the chip wasn't enabled and
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* is at power-on reset, otherwise we'll incorrectly "detect" a
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* SIL164 when there is none.
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*/
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if (!*need_post) {
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
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if (jreg & 0x80)
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ast->tx_chip_type = AST_TX_SIL164;
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}
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if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
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/*
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* On AST2300 and 2400, look the configuration set by the SoC in
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* the SOC scratch register #1 bits 11:8 (interestingly marked
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* as "reserved" in the spec)
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*/
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
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switch (jreg) {
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case 0x04:
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ast->tx_chip_type = AST_TX_SIL164;
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break;
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case 0x08:
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ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
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if (ast->dp501_fw_addr) {
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/* backup firmware */
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if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
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drmm_kfree(dev, ast->dp501_fw_addr);
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ast->dp501_fw_addr = NULL;
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}
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}
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fallthrough;
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case 0x0c:
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ast->tx_chip_type = AST_TX_DP501;
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}
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}
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/* Print stuff for diagnostic purposes */
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switch(ast->tx_chip_type) {
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case AST_TX_SIL164:
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drm_info(dev, "Using Sil164 TMDS transmitter\n");
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break;
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case AST_TX_DP501:
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drm_info(dev, "Using DP501 DisplayPort transmitter\n");
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break;
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default:
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drm_info(dev, "Analog VGA only\n");
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}
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return 0;
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}
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static int ast_get_dram_info(struct drm_device *dev)
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{
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struct device_node *np = dev->dev->of_node;
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struct ast_private *ast = to_ast_private(dev);
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uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
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uint32_t denum, num, div, ref_pll, dsel;
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switch (ast->config_mode) {
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case ast_use_dt:
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/*
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* If some properties are missing, use reasonable
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* defaults for AST2400
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*/
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if (of_property_read_u32(np, "aspeed,mcr-configuration",
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&mcr_cfg))
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mcr_cfg = 0x00000577;
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if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
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&mcr_scu_mpll))
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mcr_scu_mpll = 0x000050C0;
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if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
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&mcr_scu_strap))
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mcr_scu_strap = 0;
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break;
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case ast_use_p2a:
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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mcr_cfg = ast_read32(ast, 0x10004);
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mcr_scu_mpll = ast_read32(ast, 0x10120);
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mcr_scu_strap = ast_read32(ast, 0x10170);
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break;
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case ast_use_defaults:
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default:
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ast->dram_bus_width = 16;
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ast->dram_type = AST_DRAM_1Gx16;
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if (ast->chip == AST2500)
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ast->mclk = 800;
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else
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ast->mclk = 396;
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return 0;
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}
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if (mcr_cfg & 0x40)
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ast->dram_bus_width = 16;
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else
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ast->dram_bus_width = 32;
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if (ast->chip == AST2500) {
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switch (mcr_cfg & 0x03) {
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case 0:
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ast->dram_type = AST_DRAM_1Gx16;
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break;
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default:
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case 1:
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ast->dram_type = AST_DRAM_2Gx16;
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break;
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case 2:
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ast->dram_type = AST_DRAM_4Gx16;
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break;
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case 3:
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ast->dram_type = AST_DRAM_8Gx16;
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break;
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}
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} else if (ast->chip == AST2300 || ast->chip == AST2400) {
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switch (mcr_cfg & 0x03) {
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case 0:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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default:
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case 1:
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ast->dram_type = AST_DRAM_1Gx16;
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break;
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case 2:
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ast->dram_type = AST_DRAM_2Gx16;
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break;
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case 3:
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ast->dram_type = AST_DRAM_4Gx16;
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break;
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}
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} else {
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switch (mcr_cfg & 0x0c) {
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case 0:
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case 4:
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ast->dram_type = AST_DRAM_512Mx16;
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break;
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case 8:
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if (mcr_cfg & 0x40)
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ast->dram_type = AST_DRAM_1Gx16;
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else
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ast->dram_type = AST_DRAM_512Mx32;
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break;
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case 0xc:
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ast->dram_type = AST_DRAM_1Gx32;
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break;
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}
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}
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if (mcr_scu_strap & 0x2000)
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ref_pll = 14318;
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else
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ref_pll = 12000;
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denum = mcr_scu_mpll & 0x1f;
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num = (mcr_scu_mpll & 0x3fe0) >> 5;
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dsel = (mcr_scu_mpll & 0xc000) >> 14;
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switch (dsel) {
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case 3:
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div = 0x4;
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break;
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case 2:
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case 1:
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div = 0x2;
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break;
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default:
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div = 0x1;
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break;
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}
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ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
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return 0;
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}
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/*
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* Run this function as part of the HW device cleanup; not
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* when the DRM device gets released.
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*/
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static void ast_device_release(void *data)
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{
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struct ast_private *ast = data;
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/* enable standard VGA decode */
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ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
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}
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struct ast_private *ast_device_create(const struct drm_driver *drv,
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struct pci_dev *pdev,
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unsigned long flags)
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{
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struct drm_device *dev;
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struct ast_private *ast;
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bool need_post;
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int ret = 0;
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ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base);
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if (IS_ERR(ast))
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return ast;
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dev = &ast->base;
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pci_set_drvdata(pdev, dev);
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ast->regs = pcim_iomap(pdev, 1, 0);
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if (!ast->regs)
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return ERR_PTR(-EIO);
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/*
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* If we don't have IO space at all, use MMIO now and
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* assume the chip has MMIO enabled by default (rev 0x20
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* and higher).
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*/
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if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
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drm_info(dev, "platform has no IO space, trying MMIO\n");
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ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
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}
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/* "map" IO regs if the above hasn't done so already */
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if (!ast->ioregs) {
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ast->ioregs = pcim_iomap(pdev, 2, 0);
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if (!ast->ioregs)
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return ERR_PTR(-EIO);
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}
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ast_detect_chip(dev, &need_post);
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ret = ast_get_dram_info(dev);
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if (ret)
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return ERR_PTR(ret);
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drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
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ast->mclk, ast->dram_type, ast->dram_bus_width);
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if (need_post)
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ast_post_gpu(dev);
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ret = ast_mm_init(ast);
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if (ret)
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return ERR_PTR(ret);
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/* map reserved buffer */
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ast->dp501_fw_buf = NULL;
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if (dev->vram_mm->vram_size < pci_resource_len(pdev, 0)) {
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ast->dp501_fw_buf = pci_iomap_range(pdev, 0, dev->vram_mm->vram_size, 0);
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if (!ast->dp501_fw_buf)
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drm_info(dev, "failed to map reserved buffer!\n");
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}
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ret = ast_mode_config_init(ast);
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if (ret)
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return ERR_PTR(ret);
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ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast);
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if (ret)
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return ERR_PTR(ret);
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return ast;
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}
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