344 lines
8.2 KiB
C
344 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Root interrupt controller for the BCM2836 (Raspberry Pi 2).
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*
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* Copyright 2015 Broadcom
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*/
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#include <linux/cpu.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/irq-bcm2836.h>
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#include <asm/exception.h>
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struct bcm2836_arm_irqchip_intc {
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struct irq_domain *domain;
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void __iomem *base;
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};
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static struct bcm2836_arm_irqchip_intc intc __read_mostly;
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static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
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unsigned int bit,
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int cpu)
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{
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void __iomem *reg = intc.base + reg_offset + 4 * cpu;
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writel(readl(reg) & ~BIT(bit), reg);
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}
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static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
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unsigned int bit,
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int cpu)
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{
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void __iomem *reg = intc.base + reg_offset + 4 * cpu;
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writel(readl(reg) | BIT(bit), reg);
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}
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static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
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{
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bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
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d->hwirq - LOCAL_IRQ_CNTPSIRQ,
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smp_processor_id());
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}
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static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
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{
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bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
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d->hwirq - LOCAL_IRQ_CNTPSIRQ,
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smp_processor_id());
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}
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static struct irq_chip bcm2836_arm_irqchip_timer = {
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.name = "bcm2836-timer",
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.irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
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.irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
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};
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static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
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{
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writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
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}
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static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
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{
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writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
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}
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static struct irq_chip bcm2836_arm_irqchip_pmu = {
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.name = "bcm2836-pmu",
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.irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
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.irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
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};
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static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
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{
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}
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static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
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{
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}
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static struct irq_chip bcm2836_arm_irqchip_gpu = {
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.name = "bcm2836-gpu",
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.irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
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.irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
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};
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static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
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{
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}
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static struct irq_chip bcm2836_arm_irqchip_dummy = {
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.name = "bcm2836-dummy",
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.irq_eoi = bcm2836_arm_irqchip_dummy_op,
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};
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static int bcm2836_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct irq_chip *chip;
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switch (hw) {
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case LOCAL_IRQ_MAILBOX0:
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chip = &bcm2836_arm_irqchip_dummy;
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break;
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case LOCAL_IRQ_CNTPSIRQ:
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case LOCAL_IRQ_CNTPNSIRQ:
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case LOCAL_IRQ_CNTHPIRQ:
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case LOCAL_IRQ_CNTVIRQ:
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chip = &bcm2836_arm_irqchip_timer;
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break;
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case LOCAL_IRQ_GPU_FAST:
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chip = &bcm2836_arm_irqchip_gpu;
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break;
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case LOCAL_IRQ_PMU_FAST:
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chip = &bcm2836_arm_irqchip_pmu;
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break;
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default:
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pr_warn_once("Unexpected hw irq: %lu\n", hw);
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return -EINVAL;
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}
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irq_set_percpu_devid(irq);
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irq_domain_set_info(d, irq, hw, chip, d->host_data,
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handle_percpu_devid_irq, NULL, NULL);
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irq_set_status_flags(irq, IRQ_NOAUTOEN);
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return 0;
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}
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static void
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__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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u32 stat;
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stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
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if (stat) {
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u32 hwirq = ffs(stat) - 1;
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handle_domain_irq(intc.domain, hwirq, regs);
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}
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}
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#ifdef CONFIG_SMP
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static struct irq_domain *ipi_domain;
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static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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int cpu = smp_processor_id();
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u32 mbox_val;
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chained_irq_enter(chip, desc);
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mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
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if (mbox_val) {
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int hwirq = ffs(mbox_val) - 1;
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generic_handle_domain_irq(ipi_domain, hwirq);
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}
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chained_irq_exit(chip, desc);
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}
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static void bcm2836_arm_irqchip_ipi_ack(struct irq_data *d)
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{
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int cpu = smp_processor_id();
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writel_relaxed(BIT(d->hwirq),
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intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
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}
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static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
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const struct cpumask *mask)
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{
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int cpu;
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void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
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/*
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* Ensure that stores to normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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smp_wmb();
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for_each_cpu(cpu, mask)
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writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
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}
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static struct irq_chip bcm2836_arm_irqchip_ipi = {
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.name = "IPI",
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.irq_mask = bcm2836_arm_irqchip_dummy_op,
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.irq_unmask = bcm2836_arm_irqchip_dummy_op,
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.irq_ack = bcm2836_arm_irqchip_ipi_ack,
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.ipi_send_mask = bcm2836_arm_irqchip_ipi_send_mask,
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};
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static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
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unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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int i;
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for (i = 0; i < nr_irqs; i++) {
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irq_set_percpu_devid(virq + i);
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irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
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d->host_data,
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handle_percpu_devid_irq,
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NULL, NULL);
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}
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return 0;
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}
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static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
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unsigned int virq,
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unsigned int nr_irqs)
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{
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/* Not freeing IPIs */
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}
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static const struct irq_domain_ops ipi_domain_ops = {
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.alloc = bcm2836_arm_irqchip_ipi_alloc,
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.free = bcm2836_arm_irqchip_ipi_free,
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};
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static int bcm2836_cpu_starting(unsigned int cpu)
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{
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bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
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cpu);
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return 0;
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}
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static int bcm2836_cpu_dying(unsigned int cpu)
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{
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bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
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cpu);
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return 0;
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}
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#define BITS_PER_MBOX 32
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static void __init bcm2836_arm_irqchip_smp_init(void)
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{
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struct irq_fwspec ipi_fwspec = {
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.fwnode = intc.domain->fwnode,
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.param_count = 1,
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.param = {
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[0] = LOCAL_IRQ_MAILBOX0,
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},
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};
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int base_ipi, mux_irq;
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mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
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if (WARN_ON(mux_irq <= 0))
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return;
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ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
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BITS_PER_MBOX, &ipi_domain_ops,
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NULL);
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if (WARN_ON(!ipi_domain))
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return;
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ipi_domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
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irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
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base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, BITS_PER_MBOX,
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NUMA_NO_NODE, NULL,
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false, NULL);
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if (WARN_ON(!base_ipi))
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return;
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set_smp_ipi_range(base_ipi, BITS_PER_MBOX);
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irq_set_chained_handler_and_data(mux_irq,
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bcm2836_arm_irqchip_handle_ipi, NULL);
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/* Unmask IPIs to the boot CPU. */
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cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
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"irqchip/bcm2836:starting", bcm2836_cpu_starting,
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bcm2836_cpu_dying);
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}
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#else
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#define bcm2836_arm_irqchip_smp_init() do { } while(0)
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#endif
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static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
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.xlate = irq_domain_xlate_onetwocell,
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.map = bcm2836_map,
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};
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/*
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* The LOCAL_IRQ_CNT* timer firings are based off of the external
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* oscillator with some scaling. The firmware sets up CNTFRQ to
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* report 19.2Mhz, but doesn't set up the scaling registers.
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*/
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static void bcm2835_init_local_timer_frequency(void)
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{
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/*
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* Set the timer to source from the 19.2Mhz crystal clock (bit
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* 8 unset), and only increment by 1 instead of 2 (bit 9
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* unset).
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*/
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writel(0, intc.base + LOCAL_CONTROL);
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/*
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* Set the timer prescaler to 1:1 (timer freq = input freq *
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* 2**31 / prescaler)
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*/
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writel(0x80000000, intc.base + LOCAL_PRESCALER);
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}
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static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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intc.base = of_iomap(node, 0);
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if (!intc.base) {
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panic("%pOF: unable to map local interrupt registers\n", node);
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}
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bcm2835_init_local_timer_frequency();
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intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
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&bcm2836_arm_irqchip_intc_ops,
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NULL);
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if (!intc.domain)
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panic("%pOF: unable to create IRQ domain\n", node);
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irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);
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bcm2836_arm_irqchip_smp_init();
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set_handle_irq(bcm2836_arm_irqchip_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
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bcm2836_arm_irqchip_l1_intc_of_init);
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