134 lines
5.0 KiB
C
134 lines
5.0 KiB
C
/*
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* linux/include/asm-arm/arch-ep93xx/ep93xx-regs.h
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*/
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#ifndef __ASM_ARCH_EP93XX_REGS_H
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#define __ASM_ARCH_EP93XX_REGS_H
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/*
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* EP93xx linux memory map:
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*
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* virt phys size
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* fe800000 5M per-platform mappings
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* fed00000 80800000 2M APB
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* fef00000 80000000 1M AHB
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*/
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#define EP93XX_AHB_PHYS_BASE 0x80000000
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#define EP93XX_AHB_VIRT_BASE 0xfef00000
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#define EP93XX_AHB_SIZE 0x00100000
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#define EP93XX_APB_PHYS_BASE 0x80800000
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#define EP93XX_APB_VIRT_BASE 0xfed00000
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#define EP93XX_APB_SIZE 0x00200000
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/* AHB peripherals */
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#define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000)
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#define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000)
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#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000)
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#define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000)
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#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000)
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#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000)
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#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000)
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#define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000)
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#define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000)
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#define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000)
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#define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000)
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#define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000)
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#define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000)
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/* APB peripherals */
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#define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000)
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#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
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#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
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#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
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#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
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#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
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#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
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#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
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#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
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#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
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#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
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#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
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#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
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#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
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#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
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#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
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#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000)
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#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000)
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#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000)
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#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
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#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c)
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#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50)
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#define EP93XX_GPIO_F_INT_ACK EP93XX_GPIO_REG(0x54)
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#define EP93XX_GPIO_F_INT_ENABLE EP93XX_GPIO_REG(0x58)
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#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
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#define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90)
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#define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94)
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#define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98)
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#define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c)
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#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0)
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#define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac)
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#define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0)
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#define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4)
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#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8)
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#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
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#define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000)
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#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000)
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#define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000)
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#define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000)
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#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000)
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#define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000)
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#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000)
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#define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000)
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#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000)
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#define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000)
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#define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000)
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#define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000)
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#define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000)
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#define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000)
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#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000)
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#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
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#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
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#define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04)
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#define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000
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#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000
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#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
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#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
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#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
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#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
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#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80)
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#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000
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#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
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#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000)
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#endif
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