218 lines
5.8 KiB
C
218 lines
5.8 KiB
C
/* linux/arch/arm/mach-s3c2440/clock.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2440 Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/mutex.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <mach/hardware.h>
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#include <linux/atomic.h>
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#include <asm/irq.h>
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#include <mach/regs-clock.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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/* S3C2440 extended clock support */
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static unsigned long s3c2440_camif_upll_round(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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int div;
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if (rate > parent_rate)
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return parent_rate;
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/* note, we remove the +/- 1 calculations for the divisor */
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div = (parent_rate / rate) / 2;
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if (div < 1)
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div = 1;
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else if (div > 16)
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div = 16;
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return parent_rate / (div * 2);
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}
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static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
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rate = s3c2440_camif_upll_round(clk, rate);
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camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
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if (rate != parent_rate) {
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camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
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camdivn |= (((parent_rate / rate) / 2) - 1);
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}
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__raw_writel(camdivn, S3C2440_CAMDIVN);
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return 0;
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}
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static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
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if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
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return parent_rate;
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camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
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return parent_rate / (camdivn + 1) / 2;
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}
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/* Extra S3C2440 clocks */
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static struct clk s3c2440_clk_cam = {
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.name = "camif",
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2440_CLKCON_CAMERA,
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};
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static struct clk s3c2440_clk_cam_upll = {
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.name = "camif-upll",
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.ops = &(struct clk_ops) {
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.set_rate = s3c2440_camif_upll_setrate,
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.get_rate = s3c2440_camif_upll_getrate,
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.round_rate = s3c2440_camif_upll_round,
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},
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};
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static struct clk s3c2440_clk_ac97 = {
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.name = "ac97",
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.enable = s3c2410_clkcon_enable,
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.ctrlbit = S3C2440_CLKCON_AC97,
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};
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#define S3C24XX_VA_UART0 (S3C_VA_UART)
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#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
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#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
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#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
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static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
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{
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unsigned long ucon0, ucon1, ucon2, divisor;
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/* the fun of calculating the uart divisors on the s3c2440 */
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ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
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ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
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ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
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ucon0 &= S3C2440_UCON0_DIVMASK;
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ucon1 &= S3C2440_UCON1_DIVMASK;
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ucon2 &= S3C2440_UCON2_DIVMASK;
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if (ucon0 != 0)
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divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
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else if (ucon1 != 0)
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divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
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else if (ucon2 != 0)
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divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
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else
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/* manual calims 44, seems to be 9 */
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divisor = 9;
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return clk_get_rate(clk->parent) / divisor;
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}
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static struct clk s3c2440_clk_fclk_n = {
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.name = "fclk_n",
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.parent = &clk_f,
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.ops = &(struct clk_ops) {
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.get_rate = s3c2440_fclk_n_getrate,
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},
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};
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static struct clk_lookup s3c2440_clk_lookup[] = {
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CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
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CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
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CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
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CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
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CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
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CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
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CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
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};
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static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
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{
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struct clk *clock_upll;
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struct clk *clock_h;
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struct clk *clock_p;
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clock_p = clk_get(NULL, "pclk");
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clock_h = clk_get(NULL, "hclk");
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clock_upll = clk_get(NULL, "upll");
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if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
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printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
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return -EINVAL;
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}
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s3c2440_clk_cam.parent = clock_h;
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s3c2440_clk_ac97.parent = clock_p;
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s3c2440_clk_cam_upll.parent = clock_upll;
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s3c24xx_register_clock(&s3c2440_clk_fclk_n);
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s3c24xx_register_clock(&s3c2440_clk_ac97);
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s3c24xx_register_clock(&s3c2440_clk_cam);
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s3c24xx_register_clock(&s3c2440_clk_cam_upll);
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clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
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clk_disable(&s3c2440_clk_ac97);
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clk_disable(&s3c2440_clk_cam);
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return 0;
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}
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static struct subsys_interface s3c2440_clk_interface = {
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.name = "s3c2440_clk",
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.subsys = &s3c2440_subsys,
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.add_dev = s3c2440_clk_add,
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};
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static __init int s3c24xx_clk_init(void)
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{
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return subsys_interface_register(&s3c2440_clk_interface);
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}
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arch_initcall(s3c24xx_clk_init);
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