99 lines
2.5 KiB
ArmAsm
99 lines
2.5 KiB
ArmAsm
/*
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50)
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#define MSM_UART1_PHYS 0xA9A00000
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#define MSM_UART2_PHYS 0xA9B00000
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#define MSM_UART3_PHYS 0xA9C00000
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#elif defined(CONFIG_ARCH_MSM7X30)
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#define MSM_UART1_PHYS 0xACA00000
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#define MSM_UART2_PHYS 0xACB00000
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#define MSM_UART3_PHYS 0xACC00000
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#endif
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#if defined(CONFIG_DEBUG_MSM_UART1)
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#define MSM_DEBUG_UART_BASE 0xE1000000
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#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
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#elif defined(CONFIG_DEBUG_MSM_UART2)
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#define MSM_DEBUG_UART_BASE 0xE1000000
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#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
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#elif defined(CONFIG_DEBUG_MSM_UART3)
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#define MSM_DEBUG_UART_BASE 0xE1000000
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#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
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#endif
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#ifdef CONFIG_DEBUG_MSM8660_UART
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#define MSM_DEBUG_UART_BASE 0xF0040000
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#define MSM_DEBUG_UART_PHYS 0x19C40000
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#endif
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#ifdef CONFIG_DEBUG_MSM8960_UART
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#define MSM_DEBUG_UART_BASE 0xF0040000
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#define MSM_DEBUG_UART_PHYS 0x16440000
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#endif
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#ifdef CONFIG_DEBUG_MSM8974_UART
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#define MSM_DEBUG_UART_BASE 0xFA71E000
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#define MSM_DEBUG_UART_PHYS 0xF991E000
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#endif
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.macro addruart, rp, rv, tmp
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#ifdef MSM_DEBUG_UART_PHYS
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ldr \rp, =MSM_DEBUG_UART_PHYS
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ldr \rv, =MSM_DEBUG_UART_BASE
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#endif
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.endm
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.macro senduart, rd, rx
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#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
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@ Write the 1 character to UARTDM_TF
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str \rd, [\rx, #0x70]
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#else
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str \rd, [\rx, #0x0C]
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#endif
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.endm
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.macro waituart, rd, rx
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#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
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@ check for TX_EMT in UARTDM_SR
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ldr \rd, [\rx, #0x08]
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tst \rd, #0x08
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bne 1002f
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@ wait for TXREADY in UARTDM_ISR
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1001: ldr \rd, [\rx, #0x14]
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tst \rd, #0x80
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beq 1001b
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1002:
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@ Clear TX_READY by writing to the UARTDM_CR register
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mov \rd, #0x300
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str \rd, [\rx, #0x10]
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@ Write 0x1 to NCF register
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mov \rd, #0x1
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str \rd, [\rx, #0x40]
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@ UARTDM reg. Read to induce delay
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ldr \rd, [\rx, #0x08]
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#else
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@ wait for TX_READY
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1001: ldr \rd, [\rx, #0x08]
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tst \rd, #0x04
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beq 1001b
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#endif
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.endm
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.macro busyuart, rd, rx
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.endm
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