116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* r8a73a4 clock framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x270
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#define MPCKCR 0xe6150080
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR5 0xe6150144
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static struct clk_mapping cpg_mapping = {
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.phys = CPG_BASE,
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.len = CPG_LEN,
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};
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static struct clk extalr_clk = {
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.rate = 32768,
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.mapping = &cpg_mapping,
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};
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static struct clk extal1_clk = {
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.rate = 26000000,
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.mapping = &cpg_mapping,
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};
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static struct clk extal2_clk = {
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.rate = 48000000,
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.mapping = &cpg_mapping,
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};
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static struct clk *main_clks[] = {
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&extalr_clk,
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&extal1_clk,
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&extal2_clk,
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};
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enum {
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MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
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MSTP522,
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MSTP_NR
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
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[MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
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[MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
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[MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
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[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
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};
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static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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/* for DT */
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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};
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void __init r8a73a4_clock_init(void)
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{
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void __iomem *cpg_base, *reg;
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int k, ret = 0;
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/* fix MPCLK to EXTAL2 for now.
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* this is needed until more detailed clock topology is supported
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*/
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cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
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BUG_ON(!cpg_base);
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reg = cpg_base + (MPCKCR - CPG_BASE);
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iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
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iounmap(cpg_base);
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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shmobile_clk_init();
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else
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panic("failed to setup r8a73a4 clocks\n");
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}
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