133 lines
4.2 KiB
YAML
133 lines
4.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/N1 Pin Controller
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maintainers:
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- Gareth Williams <gareth.williams.jx@renesas.com>
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- Geert Uytterhoeven <geert+renesas@glider.be>
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a06g032-pinctrl # RZ/N1D
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- renesas,r9a06g033-pinctrl # RZ/N1S
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- const: renesas,rzn1-pinctrl # Generic RZ/N1
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reg:
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items:
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- description: GPIO Multiplexing Level1 Register Block
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- description: GPIO Multiplexing Level2 Register Block
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clocks:
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maxItems: 1
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clock-names:
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const: bus
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description:
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The bus clock, sometimes described as pclk, for register accesses.
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allOf:
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- $ref: "pinctrl.yaml#"
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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additionalProperties:
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anyOf:
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- type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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description:
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A pin multiplexing sub-node describes how to configure a set of (or a
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single) pin in some desired alternate function mode.
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A single sub-node may define several pin configurations.
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properties:
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pinmux:
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description: |
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Integer array representing pin number and pin multiplexing
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configuration.
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When a pin has to be configured in alternate function mode, use
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this property to identify the pin by its global index, and provide
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its alternate function configuration number along with it.
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When multiple pins are required to be configured as part of the
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same alternate function they shall be specified as members of the
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same argument list of a single "pinmux" property.
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Integers values in the "pinmux" argument list are assembled as:
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(PIN | MUX_FUNC << 8)
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where PIN directly corresponds to the pl_gpio pin number and
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MUX_FUNC is one of the alternate function identifiers defined in:
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<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
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These identifiers collapse the IO Multiplex Configuration Level 1
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and Level 2 numbers that are detailed in the hardware reference
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manual into a single number. The identifiers for Level 2 are simply
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offset by 10. Additional identifiers are provided to specify the
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MDIO source peripheral.
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phandle: true
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bias-disable: true
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bias-pull-up:
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description: Pull up the pin with 50 kOhm
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bias-pull-down:
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description: Pull down the pin with 50 kOhm
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bias-high-impedance: true
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drive-strength:
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enum: [ 4, 6, 8, 12 ]
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required:
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- pinmux
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additionalProperties:
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$ref: "#/additionalProperties/anyOf/0"
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- type: object
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properties:
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phandle: true
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additionalProperties:
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$ref: "#/additionalProperties/anyOf/0"
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examples:
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- |
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#include <dt-bindings/clock/r9a06g032-sysctrl.h>
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#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
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pinctrl: pinctrl@40067000 {
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compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
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reg = <0x40067000 0x1000>, <0x51000000 0x480>;
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clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
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clock-names = "bus";
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/*
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* A serial communication interface with a TX output pin and an RX
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* input pin.
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*/
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pins_uart0: pins_uart0 {
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pinmux = <
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RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
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RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
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>;
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};
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/*
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* Set the pull-up on the RXD pin of the UART.
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*/
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pins_uart0_alt: pins_uart0_alt {
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pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
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pins_uart6_rx {
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pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
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bias-pull-up;
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};
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};
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};
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