302 lines
14 KiB
C
302 lines
14 KiB
C
/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2011 Analog Devices Inc.
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* Licensed under the Clear BSD license.
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*/
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/* This file should be up to date with:
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* - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support 0.0 or 0.1 silicon - sorry */
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#if __SILICON_REVISION__ < 2
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# error will not work on BF548 silicon version 0.0, or 0.1
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#endif
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
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#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* FIFO Boot Mode Not Functional */
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#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
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/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
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/*
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* Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
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* shows that the fix itself does not cover all cases.
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*/
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#define ANOMALY_05000353 (1)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (1)
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/* External Memory Read Access Hangs Core With PLL Bypass */
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#define ANOMALY_05000360 (1)
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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#define ANOMALY_05000365 (1)
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/* Addressing Conflict between Boot ROM and Asynchronous Memory */
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#define ANOMALY_05000369 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
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/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
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#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
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/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
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#define ANOMALY_05000379 (1)
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/* Lockbox SESR Disallows Certain User Interrupts */
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#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
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#define ANOMALY_05000405 (1)
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/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
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#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
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/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
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#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
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#define ANOMALY_05000408 (1)
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/* Lockbox firmware leaves MDMA0 channel enabled */
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#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
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#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
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/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
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#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
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/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
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#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
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#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
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#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
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/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
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#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
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/* Software System Reset Corrupts PLL_LOCKCNT Register */
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#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
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/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
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#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
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/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
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#define ANOMALY_05000434 (1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
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#define ANOMALY_05000446 (1)
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/* UART IrDA Receiver Fails on Extended Bit Pulses */
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#define ANOMALY_05000447 (1)
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/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
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#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
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/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
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#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
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/* USB DMA Short Packet Data Corruption */
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#define ANOMALY_05000450 (1)
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/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
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#define ANOMALY_05000456 (1)
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/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
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#define ANOMALY_05000457 (1)
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/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
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#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
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/* USB DMA RX Data Corruption */
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#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
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/* USB TX DMA Hang */
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#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
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/* USB Rx DMA Hang */
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#define ANOMALY_05000465 (1)
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/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
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#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
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/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
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#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
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#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
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#define ANOMALY_05000483 (1)
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/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
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#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
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#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
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/* PLL May Latch Incorrect Values Coming Out of Reset */
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#define ANOMALY_05000489 (1)
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/* SPI Master Boot Can Fail Under Certain Conditions */
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#define ANOMALY_05000490 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
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#define ANOMALY_05000498 (1)
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/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
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#define ANOMALY_05000500 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
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#define ANOMALY_05000502 (1)
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/*
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* These anomalies have been "phased" out of analog.com anomaly sheets and are
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* here to show running on older silicon just isn't feasible.
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*/
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/* False Hardware Error when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
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/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
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/* TWI Slave Boot Mode Is Not Functional */
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#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
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/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
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#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
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/* Synchronous Burst Flash Boot Mode Is Not Functional */
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#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
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/* Host DMA Boot Modes Are Not Functional */
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#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
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/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
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#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
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/* Inadequate Rotary Debounce Logic Duration */
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#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
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/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
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#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
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/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
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#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
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/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
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#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
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/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
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#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
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/* USB Calibration Value Is Not Initialized */
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#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
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/* USB Calibration Value to use */
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#define ANOMALY_05000346_value 0x5411
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
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/* Data Lost when Core Reads SDH Data FIFO */
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#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
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/* PLL Status Register Is Inaccurate */
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#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
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/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
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#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
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/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
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#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
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/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
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#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
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/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
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#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
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/* 8-Bit NAND Flash Boot Mode Not Functional */
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#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
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/* Boot from OTP Memory Not Functional */
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#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
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/* bfrom_SysControl() Firmware Routine Not Functional */
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#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
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/* Programmable Preboot Settings Not Functional */
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#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
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/* CRC32 Checksum Support Not Functional */
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#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
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/* Reset Vector Must Not Be in SDRAM Memory Space */
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#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
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/* Changed Meaning of BCODE Field in SYSCR Register */
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#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
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/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
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#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
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/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
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/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
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/* Log Buffer Not Functional */
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#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
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/* Hook Routine Not Functional */
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#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
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/* Header Indirect Bit Not Functional */
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#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
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/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
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#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
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/* OTP Write Accesses Not Supported */
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#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
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/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
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#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000171 (0)
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#define ANOMALY_05000179 (0)
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#define ANOMALY_05000182 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000189 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000219 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000233 (0)
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#define ANOMALY_05000234 (0)
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#define ANOMALY_05000242 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000248 (0)
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#define ANOMALY_05000250 (0)
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#define ANOMALY_05000254 (0)
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#define ANOMALY_05000257 (0)
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#define ANOMALY_05000261 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000278 (0)
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#define ANOMALY_05000283 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000301 (0)
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#define ANOMALY_05000305 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000315 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000364 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000402 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000440 (0)
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#define ANOMALY_05000475 (0)
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#define ANOMALY_05000480 (0)
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#define ANOMALY_16000030 (0)
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#endif
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