645 lines
17 KiB
C
645 lines
17 KiB
C
/*
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* S3C24XX specific support for Samsung pinctrl/gpiolib driver.
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*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This file contains the SamsungS3C24XX specific information required by the
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* Samsung pinctrl/gpiolib driver. It also includes the implementation of
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* external gpio and wakeup interrupt support.
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include "pinctrl-samsung.h"
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#define NUM_EINT 24
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#define NUM_EINT_IRQ 6
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#define EINT_MAX_PER_GROUP 8
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#define EINTPEND_REG 0xa8
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#define EINTMASK_REG 0xa4
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#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP))
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#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88)
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#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4)
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#define EINT_LEVEL_LOW 0
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#define EINT_LEVEL_HIGH 1
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#define EINT_EDGE_FALLING 2
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#define EINT_EDGE_RISING 4
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#define EINT_EDGE_BOTH 6
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#define EINT_MASK 0xf
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static const struct samsung_pin_bank_type bank_type_1bit = {
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.fld_width = { 1, 1, },
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.reg_offset = { 0x00, 0x04, },
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};
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static const struct samsung_pin_bank_type bank_type_2bit = {
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.fld_width = { 2, 1, 2, },
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.reg_offset = { 0x00, 0x04, 0x08, },
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};
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#define PIN_BANK_A(pins, reg, id) \
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{ \
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.type = &bank_type_1bit, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define PIN_BANK_2BIT(pins, reg, id) \
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{ \
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.type = &bank_type_2bit, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
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{ \
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.type = &bank_type_2bit, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_func = 2, \
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.eint_mask = emask, \
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.eint_offset = eoffs, \
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.name = id \
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}
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/**
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* struct s3c24xx_eint_data: EINT common data
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* @drvdata: pin controller driver data
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* @domains: IRQ domains of particular EINT interrupts
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* @parents: mapped parent irqs in the main interrupt controller
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*/
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struct s3c24xx_eint_data {
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struct samsung_pinctrl_drv_data *drvdata;
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struct irq_domain *domains[NUM_EINT];
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int parents[NUM_EINT_IRQ];
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};
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/**
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* struct s3c24xx_eint_domain_data: per irq-domain data
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* @bank: pin bank related to the domain
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* @eint_data: common data
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* eint0_3_parent_only: live eints 0-3 only in the main intc
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*/
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struct s3c24xx_eint_domain_data {
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struct samsung_pin_bank *bank;
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struct s3c24xx_eint_data *eint_data;
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bool eint0_3_parent_only;
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};
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static int s3c24xx_eint_get_trigger(unsigned int type)
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{
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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return EINT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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return EINT_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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return EINT_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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return EINT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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return EINT_LEVEL_LOW;
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break;
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default:
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return -EINVAL;
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}
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}
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static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type)
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{
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/* Edge- and level-triggered interrupts need different handlers */
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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}
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static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
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struct samsung_pin_bank *bank, int pin)
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{
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const struct samsung_pin_bank_type *bank_type = bank->type;
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unsigned long flags;
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void __iomem *reg;
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u8 shift;
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u32 mask;
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u32 val;
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/* Make sure that pin is configured as interrupt */
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reg = d->virt_base + bank->pctl_offset;
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shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
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mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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spin_lock_irqsave(&bank->slock, flags);
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val = readl(reg);
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val &= ~(mask << shift);
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val |= bank->eint_func << shift;
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writel(val, reg);
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spin_unlock_irqrestore(&bank->slock, flags);
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}
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static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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int index = bank->eint_offset + data->hwirq;
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void __iomem *reg;
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int trigger;
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u8 shift;
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u32 val;
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trigger = s3c24xx_eint_get_trigger(type);
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if (trigger < 0) {
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dev_err(d->dev, "unsupported external interrupt type\n");
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return -EINVAL;
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}
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s3c24xx_eint_set_handler(data, type);
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/* Set up interrupt trigger */
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reg = d->virt_base + EINT_REG(index);
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shift = EINT_OFFS(index);
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val = readl(reg);
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val &= ~(EINT_MASK << shift);
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val |= trigger << shift;
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writel(val, reg);
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s3c24xx_eint_set_function(d, bank, data->hwirq);
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return 0;
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}
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/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
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static void s3c2410_eint0_3_ack(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
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struct s3c24xx_eint_data *eint_data = ddata->eint_data;
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int parent_irq = eint_data->parents[data->hwirq];
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struct irq_chip *parent_chip = irq_get_chip(parent_irq);
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parent_chip->irq_ack(irq_get_irq_data(parent_irq));
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}
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static void s3c2410_eint0_3_mask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
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struct s3c24xx_eint_data *eint_data = ddata->eint_data;
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int parent_irq = eint_data->parents[data->hwirq];
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struct irq_chip *parent_chip = irq_get_chip(parent_irq);
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parent_chip->irq_mask(irq_get_irq_data(parent_irq));
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}
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static void s3c2410_eint0_3_unmask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
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struct s3c24xx_eint_data *eint_data = ddata->eint_data;
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int parent_irq = eint_data->parents[data->hwirq];
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struct irq_chip *parent_chip = irq_get_chip(parent_irq);
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parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
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}
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static struct irq_chip s3c2410_eint0_3_chip = {
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.name = "s3c2410-eint0_3",
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.irq_ack = s3c2410_eint0_3_ack,
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.irq_mask = s3c2410_eint0_3_mask,
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.irq_unmask = s3c2410_eint0_3_unmask,
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.irq_set_type = s3c24xx_eint_type,
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};
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static void s3c2410_demux_eint0_3(struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
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unsigned int virq;
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/* the first 4 eints have a simple 1 to 1 mapping */
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virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
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/* Something must be really wrong if an unmapped EINT is unmasked */
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BUG_ON(!virq);
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generic_handle_irq(virq);
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}
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/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
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static void s3c2412_eint0_3_ack(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long bitval = 1UL << data->hwirq;
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writel(bitval, d->virt_base + EINTPEND_REG);
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}
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static void s3c2412_eint0_3_mask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long mask;
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mask = readl(d->virt_base + EINTMASK_REG);
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mask |= (1UL << data->hwirq);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static void s3c2412_eint0_3_unmask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long mask;
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mask = readl(d->virt_base + EINTMASK_REG);
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mask &= ~(1UL << data->hwirq);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static struct irq_chip s3c2412_eint0_3_chip = {
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.name = "s3c2412-eint0_3",
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.irq_ack = s3c2412_eint0_3_ack,
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.irq_mask = s3c2412_eint0_3_mask,
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.irq_unmask = s3c2412_eint0_3_unmask,
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.irq_set_type = s3c24xx_eint_type,
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};
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static void s3c2412_demux_eint0_3(struct irq_desc *desc)
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{
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struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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unsigned int virq;
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chained_irq_enter(chip, desc);
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/* the first 4 eints have a simple 1 to 1 mapping */
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virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
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/* Something must be really wrong if an unmapped EINT is unmasked */
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BUG_ON(!virq);
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generic_handle_irq(virq);
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chained_irq_exit(chip, desc);
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}
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/* Handling of all other eints */
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static void s3c24xx_eint_ack(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = bank->eint_offset + data->hwirq;
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writel(1UL << index, d->virt_base + EINTPEND_REG);
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}
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static void s3c24xx_eint_mask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = bank->eint_offset + data->hwirq;
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unsigned long mask;
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mask = readl(d->virt_base + EINTMASK_REG);
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mask |= (1UL << index);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static void s3c24xx_eint_unmask(struct irq_data *data)
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{
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned char index = bank->eint_offset + data->hwirq;
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unsigned long mask;
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mask = readl(d->virt_base + EINTMASK_REG);
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mask &= ~(1UL << index);
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writel(mask, d->virt_base + EINTMASK_REG);
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}
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static struct irq_chip s3c24xx_eint_chip = {
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.name = "s3c-eint",
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.irq_ack = s3c24xx_eint_ack,
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.irq_mask = s3c24xx_eint_mask,
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.irq_unmask = s3c24xx_eint_unmask,
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.irq_set_type = s3c24xx_eint_type,
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};
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static inline void s3c24xx_demux_eint(struct irq_desc *desc,
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u32 offset, u32 range)
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{
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struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct samsung_pinctrl_drv_data *d = data->drvdata;
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unsigned int pend, mask;
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chained_irq_enter(chip, desc);
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pend = readl(d->virt_base + EINTPEND_REG);
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mask = readl(d->virt_base + EINTMASK_REG);
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pend &= ~mask;
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pend &= range;
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while (pend) {
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unsigned int virq, irq;
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irq = __ffs(pend);
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pend &= ~(1 << irq);
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virq = irq_linear_revmap(data->domains[irq], irq - offset);
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/* Something is really wrong if an unmapped EINT is unmasked */
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BUG_ON(!virq);
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generic_handle_irq(virq);
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}
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chained_irq_exit(chip, desc);
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}
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static void s3c24xx_demux_eint4_7(struct irq_desc *desc)
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{
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s3c24xx_demux_eint(desc, 0, 0xf0);
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}
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static void s3c24xx_demux_eint8_23(struct irq_desc *desc)
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{
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s3c24xx_demux_eint(desc, 8, 0xffff00);
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}
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static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
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s3c2410_demux_eint0_3,
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s3c2410_demux_eint0_3,
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s3c2410_demux_eint0_3,
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s3c2410_demux_eint0_3,
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s3c24xx_demux_eint4_7,
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s3c24xx_demux_eint8_23,
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};
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static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
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s3c2412_demux_eint0_3,
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s3c2412_demux_eint0_3,
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s3c2412_demux_eint0_3,
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s3c2412_demux_eint0_3,
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s3c24xx_demux_eint4_7,
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s3c24xx_demux_eint8_23,
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};
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static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct s3c24xx_eint_domain_data *ddata = h->host_data;
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struct samsung_pin_bank *bank = ddata->bank;
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if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
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return -EINVAL;
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if (hw <= 3) {
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if (ddata->eint0_3_parent_only)
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irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
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handle_edge_irq);
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else
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irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
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handle_edge_irq);
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} else {
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irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
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handle_edge_irq);
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}
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irq_set_chip_data(virq, bank);
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return 0;
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}
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static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
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.map = s3c24xx_gpf_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct s3c24xx_eint_domain_data *ddata = h->host_data;
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struct samsung_pin_bank *bank = ddata->bank;
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if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
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return -EINVAL;
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irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
|
|
irq_set_chip_data(virq, bank);
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
|
|
.map = s3c24xx_gpg_irq_map,
|
|
.xlate = irq_domain_xlate_twocell,
|
|
};
|
|
|
|
static const struct of_device_id s3c24xx_eint_irq_ids[] = {
|
|
{ .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
|
|
{ .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
|
|
{ }
|
|
};
|
|
|
|
static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
|
|
{
|
|
struct device *dev = d->dev;
|
|
const struct of_device_id *match;
|
|
struct device_node *eint_np = NULL;
|
|
struct device_node *np;
|
|
struct samsung_pin_bank *bank;
|
|
struct s3c24xx_eint_data *eint_data;
|
|
const struct irq_domain_ops *ops;
|
|
unsigned int i;
|
|
bool eint0_3_parent_only;
|
|
irq_flow_handler_t *handlers;
|
|
|
|
for_each_child_of_node(dev->of_node, np) {
|
|
match = of_match_node(s3c24xx_eint_irq_ids, np);
|
|
if (match) {
|
|
eint_np = np;
|
|
eint0_3_parent_only = (bool)match->data;
|
|
break;
|
|
}
|
|
}
|
|
if (!eint_np)
|
|
return -ENODEV;
|
|
|
|
eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
|
|
if (!eint_data)
|
|
return -ENOMEM;
|
|
|
|
eint_data->drvdata = d;
|
|
|
|
handlers = eint0_3_parent_only ? s3c2410_eint_handlers
|
|
: s3c2412_eint_handlers;
|
|
for (i = 0; i < NUM_EINT_IRQ; ++i) {
|
|
unsigned int irq;
|
|
|
|
irq = irq_of_parse_and_map(eint_np, i);
|
|
if (!irq) {
|
|
dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
|
|
return -ENXIO;
|
|
}
|
|
|
|
eint_data->parents[i] = irq;
|
|
irq_set_chained_handler_and_data(irq, handlers[i], eint_data);
|
|
}
|
|
|
|
bank = d->pin_banks;
|
|
for (i = 0; i < d->nr_banks; ++i, ++bank) {
|
|
struct s3c24xx_eint_domain_data *ddata;
|
|
unsigned int mask;
|
|
unsigned int irq;
|
|
unsigned int pin;
|
|
|
|
if (bank->eint_type != EINT_TYPE_WKUP)
|
|
continue;
|
|
|
|
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
|
|
if (!ddata)
|
|
return -ENOMEM;
|
|
|
|
ddata->bank = bank;
|
|
ddata->eint_data = eint_data;
|
|
ddata->eint0_3_parent_only = eint0_3_parent_only;
|
|
|
|
ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
|
|
: &s3c24xx_gpg_irq_ops;
|
|
|
|
bank->irq_domain = irq_domain_add_linear(bank->of_node,
|
|
bank->nr_pins, ops, ddata);
|
|
if (!bank->irq_domain) {
|
|
dev_err(dev, "wkup irq domain add failed\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
irq = bank->eint_offset;
|
|
mask = bank->eint_mask;
|
|
for (pin = 0; mask; ++pin, mask >>= 1) {
|
|
if (irq >= NUM_EINT)
|
|
break;
|
|
if (!(mask & 1))
|
|
continue;
|
|
eint_data->domains[irq] = bank->irq_domain;
|
|
++irq;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = {
|
|
PIN_BANK_A(23, 0x000, "gpa"),
|
|
PIN_BANK_2BIT(11, 0x010, "gpb"),
|
|
PIN_BANK_2BIT(16, 0x020, "gpc"),
|
|
PIN_BANK_2BIT(16, 0x030, "gpd"),
|
|
PIN_BANK_2BIT(16, 0x040, "gpe"),
|
|
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
|
|
PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
|
|
PIN_BANK_2BIT(11, 0x070, "gph"),
|
|
PIN_BANK_2BIT(13, 0x080, "gpj"),
|
|
};
|
|
|
|
const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = {
|
|
{
|
|
.pin_banks = s3c2412_pin_banks,
|
|
.nr_banks = ARRAY_SIZE(s3c2412_pin_banks),
|
|
.eint_wkup_init = s3c24xx_eint_init,
|
|
},
|
|
};
|
|
|
|
static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = {
|
|
PIN_BANK_A(27, 0x000, "gpa"),
|
|
PIN_BANK_2BIT(11, 0x010, "gpb"),
|
|
PIN_BANK_2BIT(16, 0x020, "gpc"),
|
|
PIN_BANK_2BIT(16, 0x030, "gpd"),
|
|
PIN_BANK_2BIT(16, 0x040, "gpe"),
|
|
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
|
|
PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
|
|
PIN_BANK_2BIT(15, 0x070, "gph"),
|
|
PIN_BANK_2BIT(16, 0x0e0, "gpk"),
|
|
PIN_BANK_2BIT(14, 0x0f0, "gpl"),
|
|
PIN_BANK_2BIT(2, 0x100, "gpm"),
|
|
};
|
|
|
|
const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = {
|
|
{
|
|
.pin_banks = s3c2416_pin_banks,
|
|
.nr_banks = ARRAY_SIZE(s3c2416_pin_banks),
|
|
.eint_wkup_init = s3c24xx_eint_init,
|
|
},
|
|
};
|
|
|
|
static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = {
|
|
PIN_BANK_A(25, 0x000, "gpa"),
|
|
PIN_BANK_2BIT(11, 0x010, "gpb"),
|
|
PIN_BANK_2BIT(16, 0x020, "gpc"),
|
|
PIN_BANK_2BIT(16, 0x030, "gpd"),
|
|
PIN_BANK_2BIT(16, 0x040, "gpe"),
|
|
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
|
|
PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
|
|
PIN_BANK_2BIT(11, 0x070, "gph"),
|
|
PIN_BANK_2BIT(13, 0x0d0, "gpj"),
|
|
};
|
|
|
|
const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = {
|
|
{
|
|
.pin_banks = s3c2440_pin_banks,
|
|
.nr_banks = ARRAY_SIZE(s3c2440_pin_banks),
|
|
.eint_wkup_init = s3c24xx_eint_init,
|
|
},
|
|
};
|
|
|
|
static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = {
|
|
PIN_BANK_A(28, 0x000, "gpa"),
|
|
PIN_BANK_2BIT(11, 0x010, "gpb"),
|
|
PIN_BANK_2BIT(16, 0x020, "gpc"),
|
|
PIN_BANK_2BIT(16, 0x030, "gpd"),
|
|
PIN_BANK_2BIT(16, 0x040, "gpe"),
|
|
PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
|
|
PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
|
|
PIN_BANK_2BIT(15, 0x070, "gph"),
|
|
PIN_BANK_2BIT(16, 0x0d0, "gpj"),
|
|
PIN_BANK_2BIT(16, 0x0e0, "gpk"),
|
|
PIN_BANK_2BIT(15, 0x0f0, "gpl"),
|
|
PIN_BANK_2BIT(2, 0x100, "gpm"),
|
|
};
|
|
|
|
const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = {
|
|
{
|
|
.pin_banks = s3c2450_pin_banks,
|
|
.nr_banks = ARRAY_SIZE(s3c2450_pin_banks),
|
|
.eint_wkup_init = s3c24xx_eint_init,
|
|
},
|
|
};
|