98 lines
1.9 KiB
Plaintext
98 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Hardkernel Odroid XU4 board device tree source
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*
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* Copyright (c) 2015 Krzysztof Kozlowski
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* Copyright (c) 2014 Collabora Ltd.
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* Copyright (c) 2013-2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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/dts-v1/;
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#include <dt-bindings/sound/samsung-i2s.h>
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#include "exynos5422-odroidxu3-common.dtsi"
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/ {
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model = "Hardkernel Odroid XU4";
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compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \
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"samsung,exynos5";
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pwmleds {
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compatible = "pwm-leds";
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blueled {
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label = "blue:heartbeat";
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pwms = <&pwm 2 2000000 0>;
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pwm-names = "pwm2";
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max_brightness = <255>;
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linux,default-trigger = "heartbeat";
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};
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};
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sound: sound {
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compatible = "samsung,odroid-xu3-audio";
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model = "Odroid-XU4";
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assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
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<&clock CLK_MOUT_EPLL>,
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<&clock CLK_MOUT_MAU_EPLL>,
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<&clock CLK_MOUT_USER_MAU_EPLL>,
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<&clock_audss EXYNOS_MOUT_AUDSS>,
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<&clock_audss EXYNOS_MOUT_I2S>,
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<&clock_audss EXYNOS_DOUT_SRP>,
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<&clock_audss EXYNOS_DOUT_AUD_BUS>,
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<&clock_audss EXYNOS_DOUT_I2S>;
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assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
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<&clock CLK_FOUT_EPLL>,
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<&clock CLK_MOUT_EPLL>,
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<&clock CLK_MOUT_MAU_EPLL>,
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<&clock CLK_MAU_EPLL>,
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<&clock_audss EXYNOS_MOUT_AUDSS>;
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assigned-clock-rates = <0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<196608001>,
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<(196608002 / 2)>,
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<196608000>;
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cpu {
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sound-dai = <&i2s0 0>;
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};
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codec {
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sound-dai = <&hdmi>;
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};
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};
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};
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&clock_audss {
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assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
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<&clock CLK_FOUT_EPLL>;
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assigned-clock-rates = <(196608000 / 256)>,
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<196608000>;
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};
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&i2s0 {
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status = "okay";
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};
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&pwm {
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/*
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* PWM 0 -- fan
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* PWM 2 -- Blue LED
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*/
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pinctrl-0 = <&pwm0_out &pwm2_out>;
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pinctrl-names = "default";
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samsung,pwm-outputs = <0>, <2>;
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status = "okay";
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};
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&usbdrd_dwc3_1 {
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dr_mode = "host";
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};
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