376 lines
9.4 KiB
C
376 lines
9.4 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#ifndef __ASM_KVM_BOOK3S_64_H__
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#define __ASM_KVM_BOOK3S_64_H__
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#include <asm/book3s/64/mmu-hash.h>
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/* Power architecture requires HPT is at least 256kiB, at most 64TiB */
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#define PPC_MIN_HPT_ORDER 18
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#define PPC_MAX_HPT_ORDER 46
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#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
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static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
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{
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preempt_disable();
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return &get_paca()->shadow_vcpu;
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}
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static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
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{
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preempt_enable();
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}
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#endif
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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static inline bool kvm_is_radix(struct kvm *kvm)
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{
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return kvm->arch.radix;
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}
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#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
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#endif
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/*
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* We use a lock bit in HPTE dword 0 to synchronize updates and
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* accesses to each HPTE, and another bit to indicate non-present
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* HPTEs.
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*/
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#define HPTE_V_HVLOCK 0x40UL
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#define HPTE_V_ABSENT 0x20UL
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/*
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* We use this bit in the guest_rpte field of the revmap entry
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* to indicate a modified HPTE.
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*/
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#define HPTE_GR_MODIFIED (1ul << 62)
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/* These bits are reserved in the guest view of the HPTE */
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#define HPTE_GR_RESERVED HPTE_GR_MODIFIED
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static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
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{
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unsigned long tmp, old;
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__be64 be_lockbit, be_bits;
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/*
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* We load/store in native endian, but the HTAB is in big endian. If
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* we byte swap all data we apply on the PTE we're implicitly correct
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* again.
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*/
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be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
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be_bits = cpu_to_be64(bits);
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asm volatile(" ldarx %0,0,%2\n"
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" and. %1,%0,%3\n"
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" bne 2f\n"
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" or %0,%0,%4\n"
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" stdcx. %0,0,%2\n"
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" beq+ 2f\n"
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" mr %1,%3\n"
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"2: isync"
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: "=&r" (tmp), "=&r" (old)
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: "r" (hpte), "r" (be_bits), "r" (be_lockbit)
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: "cc", "memory");
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return old == 0;
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}
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static inline void unlock_hpte(__be64 *hpte, unsigned long hpte_v)
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{
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hpte_v &= ~HPTE_V_HVLOCK;
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asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
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hpte[0] = cpu_to_be64(hpte_v);
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}
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/* Without barrier */
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static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)
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{
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hpte_v &= ~HPTE_V_HVLOCK;
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hpte[0] = cpu_to_be64(hpte_v);
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}
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static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
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unsigned long pte_index)
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{
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int i, b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
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unsigned int penc;
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unsigned long rb = 0, va_low, sllp;
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unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
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if (v & HPTE_V_LARGE) {
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i = hpte_page_sizes[lp];
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b_psize = i & 0xf;
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a_psize = i >> 4;
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}
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/*
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* Ignore the top 14 bits of va
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* v have top two bits covering segment size, hence move
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* by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
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* AVA field in v also have the lower 23 bits ignored.
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* For base page size 4K we need 14 .. 65 bits (so need to
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* collect extra 11 bits)
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* For others we need 14..14+i
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*/
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/* This covers 14..54 bits of va*/
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rb = (v & ~0x7fUL) << 16; /* AVA field */
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/*
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* AVA in v had cleared lower 23 bits. We need to derive
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* that from pteg index
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*/
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va_low = pte_index >> 3;
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if (v & HPTE_V_SECONDARY)
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va_low = ~va_low;
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/*
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* get the vpn bits from va_low using reverse of hashing.
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* In v we have va with 23 bits dropped and then left shifted
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* HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
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* right shift it with (SID_SHIFT - (23 - 7))
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*/
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if (!(v & HPTE_V_1TB_SEG))
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va_low ^= v >> (SID_SHIFT - 16);
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else
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va_low ^= v >> (SID_SHIFT_1T - 16);
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va_low &= 0x7ff;
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switch (b_psize) {
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case MMU_PAGE_4K:
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sllp = get_sllp_encoding(a_psize);
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rb |= sllp << 5; /* AP field */
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rb |= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */
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break;
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default:
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{
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int aval_shift;
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/*
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* remaining bits of AVA/LP fields
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* Also contain the rr bits of LP
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*/
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rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
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/*
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* Now clear not needed LP bits based on actual psize
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*/
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rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
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/*
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* AVAL field 58..77 - base_page_shift bits of va
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* we have space for 58..64 bits, Missing bits should
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* be zero filled. +1 is to take care of L bit shift
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*/
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aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;
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rb |= ((va_low << aval_shift) & 0xfe);
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rb |= 1; /* L field */
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penc = mmu_psize_defs[b_psize].penc[a_psize];
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rb |= penc << 12; /* LP field */
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break;
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}
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}
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rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */
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return rb;
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}
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static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
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{
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return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
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}
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static inline int hpte_is_writable(unsigned long ptel)
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{
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unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
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return pp != PP_RXRX && pp != PP_RXXX;
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}
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static inline unsigned long hpte_make_readonly(unsigned long ptel)
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{
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if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
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ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
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else
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ptel |= PP_RXRX;
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return ptel;
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}
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static inline bool hpte_cache_flags_ok(unsigned long hptel, bool is_ci)
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{
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unsigned int wimg = hptel & HPTE_R_WIMG;
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/* Handle SAO */
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if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
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cpu_has_feature(CPU_FTR_ARCH_206))
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wimg = HPTE_R_M;
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if (!is_ci)
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return wimg == HPTE_R_M;
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/*
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* if host is mapped cache inhibited, make sure hptel also have
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* cache inhibited.
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*/
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if (wimg & HPTE_R_W) /* FIXME!! is this ok for all guest. ? */
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return false;
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return !!(wimg & HPTE_R_I);
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}
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/*
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* If it's present and writable, atomically set dirty and referenced bits and
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* return the PTE, otherwise return 0.
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*/
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static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing)
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{
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pte_t old_pte, new_pte = __pte(0);
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while (1) {
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/*
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* Make sure we don't reload from ptep
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*/
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old_pte = READ_ONCE(*ptep);
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/*
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* wait until H_PAGE_BUSY is clear then set it atomically
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*/
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if (unlikely(pte_val(old_pte) & H_PAGE_BUSY)) {
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cpu_relax();
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continue;
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}
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/* If pte is not present return None */
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if (unlikely(!(pte_val(old_pte) & _PAGE_PRESENT)))
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return __pte(0);
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new_pte = pte_mkyoung(old_pte);
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if (writing && pte_write(old_pte))
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new_pte = pte_mkdirty(new_pte);
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if (pte_xchg(ptep, old_pte, new_pte))
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break;
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}
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return new_pte;
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}
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static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
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{
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if (key)
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return PP_RWRX <= pp && pp <= PP_RXRX;
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return true;
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}
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static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
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{
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if (key)
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return pp == PP_RWRW;
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return pp <= PP_RWRW;
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}
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static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
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{
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unsigned long skey;
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skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
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((hpte_r & HPTE_R_KEY_LO) >> 9);
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return (amr >> (62 - 2 * skey)) & 3;
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}
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static inline void lock_rmap(unsigned long *rmap)
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{
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do {
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while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
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cpu_relax();
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} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
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}
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static inline void unlock_rmap(unsigned long *rmap)
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{
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__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
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}
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static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
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unsigned long pagesize)
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{
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unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
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if (pagesize <= PAGE_SIZE)
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return true;
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return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
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}
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/*
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* This works for 4k, 64k and 16M pages on POWER7,
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* and 4k and 16M pages on PPC970.
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*/
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static inline unsigned long slb_pgsize_encoding(unsigned long psize)
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{
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unsigned long senc = 0;
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if (psize > 0x1000) {
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senc = SLB_VSID_L;
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if (psize == 0x10000)
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senc |= SLB_VSID_LP_01;
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}
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return senc;
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}
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static inline int is_vrma_hpte(unsigned long hpte_v)
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{
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return (hpte_v & ~0xffffffUL) ==
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(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
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}
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/*
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* Note modification of an HPTE; set the HPTE modified bit
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* if anyone is interested.
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*/
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static inline void note_hpte_modification(struct kvm *kvm,
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struct revmap_entry *rev)
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{
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if (atomic_read(&kvm->arch.hpte_mod_interest))
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rev->guest_rpte |= HPTE_GR_MODIFIED;
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}
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/*
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* Like kvm_memslots(), but for use in real mode when we can't do
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* any RCU stuff (since the secondary threads are offline from the
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* kernel's point of view), and we can't print anything.
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* Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
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*/
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static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
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{
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return rcu_dereference_raw_notrace(kvm->memslots[0]);
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}
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extern void kvmppc_mmu_debugfs_init(struct kvm *kvm);
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extern void kvmhv_rm_send_ipi(int cpu);
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static inline unsigned long kvmppc_hpt_npte(struct kvm_hpt_info *hpt)
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{
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/* HPTEs are 2**4 bytes long */
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return 1UL << (hpt->order - 4);
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}
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static inline unsigned long kvmppc_hpt_mask(struct kvm_hpt_info *hpt)
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{
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/* 128 (2**7) bytes in each HPTEG */
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return (1UL << (hpt->order - 7)) - 1;
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}
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#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
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#endif /* __ASM_KVM_BOOK3S_64_H__ */
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