122 lines
2.7 KiB
C
122 lines
2.7 KiB
C
#ifndef __ASM_SH_HW_IRQ_H
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#define __ASM_SH_HW_IRQ_H
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#include <linux/init.h>
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#include <asm/atomic.h>
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extern atomic_t irq_err_count;
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struct intc2_data {
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unsigned short irq;
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unsigned char ipr_offset, ipr_shift;
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unsigned char msk_offset, msk_shift;
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unsigned char priority;
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};
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struct intc2_desc {
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unsigned long prio_base;
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unsigned long msk_base;
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unsigned long mskclr_base;
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struct intc2_data *intc2_data;
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unsigned int nr_irqs;
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struct irq_chip chip;
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};
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void register_intc2_controller(struct intc2_desc *);
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struct ipr_data {
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unsigned char irq;
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unsigned char ipr_idx; /* Index for the IPR registered */
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unsigned char shift; /* Number of bits to shift the data */
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unsigned char priority; /* The priority */
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};
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struct ipr_desc {
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unsigned long *ipr_offsets;
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unsigned int nr_offsets;
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struct ipr_data *ipr_data;
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unsigned int nr_irqs;
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struct irq_chip chip;
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};
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void register_ipr_controller(struct ipr_desc *);
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/*
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* Enable individual interrupt mode for external IPR IRQs.
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*/
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void __init ipr_irq_enable_irlm(void);
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typedef unsigned char intc_enum;
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struct intc_vect {
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intc_enum enum_id;
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unsigned short vect;
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};
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#define INTC_VECT(enum_id, vect) { enum_id, vect }
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struct intc_prio {
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intc_enum enum_id;
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unsigned char priority;
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};
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#define INTC_PRIO(enum_id, prio) { enum_id, prio }
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struct intc_group {
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intc_enum enum_id;
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intc_enum *enum_ids;
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};
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#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
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struct intc_mask_reg {
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unsigned long set_reg, clr_reg, reg_width;
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intc_enum enum_ids[32];
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};
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struct intc_prio_reg {
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unsigned long reg, reg_width, field_width;
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intc_enum enum_ids[16];
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};
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struct intc_sense_reg {
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unsigned long reg, reg_width, field_width;
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intc_enum enum_ids[16];
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};
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struct intc_desc {
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struct intc_vect *vectors;
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unsigned int nr_vectors;
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struct intc_group *groups;
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unsigned int nr_groups;
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struct intc_prio *priorities;
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unsigned int nr_priorities;
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struct intc_mask_reg *mask_regs;
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unsigned int nr_mask_regs;
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struct intc_prio_reg *prio_regs;
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unsigned int nr_prio_regs;
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struct intc_sense_reg *sense_regs;
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unsigned int nr_sense_regs;
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struct irq_chip chip;
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};
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#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
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#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
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priorities, mask_regs, prio_regs, sense_regs) \
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struct intc_desc symbol = { \
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_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
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_INTC_ARRAY(priorities), \
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_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
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_INTC_ARRAY(sense_regs), \
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.chip.name = chipname, \
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}
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void __init register_intc_controller(struct intc_desc *desc);
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void __init plat_irq_setup(void);
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enum { IRQ_MODE_IRQ, IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
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void __init plat_irq_setup_pins(int mode);
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#endif /* __ASM_SH_HW_IRQ_H */
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