207 lines
6.1 KiB
C
207 lines
6.1 KiB
C
/*
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* OMAP4 PRM instance functions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "iomap.h"
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#include "common.h"
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#include "prcm-common.h"
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#include "prm44xx.h"
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#include "prm54xx.h"
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#include "prm7xx.h"
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#include "prminst44xx.h"
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#include "prm-regbits-44xx.h"
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#include "prcm44xx.h"
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#include "prcm43xx.h"
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#include "prcm_mpu44xx.h"
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#include "soc.h"
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static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
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static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
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/**
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* omap_prm_base_init - Populates the prm partitions
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*
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* Populates the base addresses of the _prm_bases
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* array used for read/write of prm module registers.
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*/
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void omap_prm_base_init(void)
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{
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_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
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_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
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}
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s32 omap4_prmst_get_prm_dev_inst(void)
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{
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if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
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return prm_dev_inst;
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/* This cannot be done way early at boot.. as things are not setup */
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if (cpu_is_omap44xx())
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prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
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else if (soc_is_omap54xx())
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prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
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else if (soc_is_dra7xx())
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prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
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else if (soc_is_am43xx())
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prm_dev_inst = AM43XX_PRM_DEVICE_INST;
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return prm_dev_inst;
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}
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/* Read a register in a PRM instance */
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u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_prm_bases[part]);
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return readl_relaxed(_prm_bases[part] + inst + idx);
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}
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/* Write into a register in a PRM instance */
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void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_prm_bases[part]);
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writel_relaxed(val, _prm_bases[part] + inst + idx);
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}
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/* Read-modify-write a register in PRM. Caller must lock */
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u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
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u16 idx)
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{
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u32 v;
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v = omap4_prminst_read_inst_reg(part, inst, idx);
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v &= ~mask;
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v |= bits;
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omap4_prminst_write_inst_reg(v, part, inst, idx);
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return v;
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}
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/*
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* Address offset (in bytes) between the reset control and the reset
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* status registers: 4 bytes on OMAP4
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*/
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#define OMAP4_RST_CTRL_ST_OFFSET 4
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/**
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* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to check
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*
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* Returns 1 if the (sub)module hardreset line is currently asserted,
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* 0 if the (sub)module hardreset line is not currently asserted, or
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* -EINVAL upon parameter error.
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*/
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int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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u32 v;
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v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
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v &= 1 << shift;
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v >>= shift;
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return v;
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}
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/**
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* omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to assert
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* place the submodule into reset. Returns 0 upon success or -EINVAL
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* upon an argument error.
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*/
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int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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u32 mask = 1 << shift;
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omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
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return 0;
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}
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/**
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* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
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* wait
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to deassert
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* take the submodule out of reset and wait until the PRCM indicates
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* that the reset has completed before returning. Returns 0 upon success or
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* -EINVAL upon an argument error, -EEXIST if the submodule was already out
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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int c;
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u32 mask = 1 << shift;
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u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
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/* Check the current status to avoid de-asserting the line twice */
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if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
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rstctrl_offs) == 0)
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
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rstst_offs);
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/* de-assert the reset control line */
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omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
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/* wait the status to be set */
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omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
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rstst_offs),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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}
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void omap4_prminst_global_warm_sw_reset(void)
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{
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u32 v;
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s32 inst = omap4_prmst_get_prm_dev_inst();
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if (inst == PRM_INSTANCE_UNKNOWN)
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return;
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v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
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OMAP4_PRM_RSTCTRL_OFFSET);
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v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
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omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
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inst, OMAP4_PRM_RSTCTRL_OFFSET);
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/* OCP barrier */
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v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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inst, OMAP4_PRM_RSTCTRL_OFFSET);
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}
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