180 lines
3.8 KiB
C
180 lines
3.8 KiB
C
/*
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* arch/arm/mach-tegra/include/mach/uncompress.h
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2011 Google, Inc.
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* Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Erik Gilling <konkers@google.com>
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* Doug Anderson <dianders@chromium.org>
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* Stephen Warren <swarren@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_UNCOMPRESS_H
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#define __MACH_TEGRA_UNCOMPRESS_H
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#include <linux/types.h>
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#include <linux/serial_reg.h>
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#include "../../iomap.h"
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#define BIT(x) (1 << (x))
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#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
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#define DEBUG_UART_SHIFT 2
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volatile u8 *uart;
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static void putc(int c)
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{
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if (uart == NULL)
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return;
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while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
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barrier();
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uart[UART_TX << DEBUG_UART_SHIFT] = c;
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}
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static inline void flush(void)
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{
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}
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static const struct {
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u32 base;
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u32 reset_reg;
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u32 clock_reg;
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u32 bit;
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} uarts[] = {
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{
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TEGRA_UARTA_BASE,
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TEGRA_CLK_RESET_BASE + 0x04,
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TEGRA_CLK_RESET_BASE + 0x10,
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6,
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},
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{
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TEGRA_UARTB_BASE,
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TEGRA_CLK_RESET_BASE + 0x04,
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TEGRA_CLK_RESET_BASE + 0x10,
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7,
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},
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{
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TEGRA_UARTC_BASE,
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TEGRA_CLK_RESET_BASE + 0x08,
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TEGRA_CLK_RESET_BASE + 0x14,
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23,
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},
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{
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TEGRA_UARTD_BASE,
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TEGRA_CLK_RESET_BASE + 0x0c,
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TEGRA_CLK_RESET_BASE + 0x18,
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1,
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},
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{
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TEGRA_UARTE_BASE,
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TEGRA_CLK_RESET_BASE + 0x0c,
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TEGRA_CLK_RESET_BASE + 0x18,
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2,
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},
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};
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static inline bool uart_clocked(int i)
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{
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if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit))
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return false;
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if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit)))
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return false;
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return true;
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}
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#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
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int auto_odmdata(void)
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{
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volatile u32 *pmc = (volatile u32 *)TEGRA_PMC_BASE;
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u32 odmdata = pmc[0xa0 / 4];
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/*
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* Bits 19:18 are the console type: 0=default, 1=none, 2==DCC, 3==UART
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* Some boards apparently swap the last two values, but we don't have
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* any way of catering for that here, so we just accept either. If this
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* doesn't make sense for your board, just don't enable this feature.
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*
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* Bits 17:15 indicate the UART to use, 0/1/2/3/4 are UART A/B/C/D/E.
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*/
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switch ((odmdata >> 18) & 3) {
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case 2:
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case 3:
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break;
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default:
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return -1;
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}
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return (odmdata >> 15) & 7;
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}
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#endif
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/*
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* Setup before decompression. This is where we do UART selection for
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* earlyprintk and init the uart_base register.
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*/
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static inline void arch_decomp_setup(void)
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{
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int uart_id;
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volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
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u32 chip, div;
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#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
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uart_id = auto_odmdata();
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#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
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uart_id = 0;
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#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
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uart_id = 1;
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#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
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uart_id = 2;
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#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
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uart_id = 3;
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#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
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uart_id = 4;
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#endif
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if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
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!uart_clocked(uart_id))
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uart = NULL;
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else
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uart = (volatile u8 *)uarts[uart_id].base;
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if (uart == NULL)
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return;
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chip = (apb_misc[0x804 / 4] >> 8) & 0xff;
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if (chip == 0x20)
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div = 0x0075;
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else
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div = 0x00dd;
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uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
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uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff;
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uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8;
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uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
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}
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static inline void arch_decomp_wdog(void)
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{
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}
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#endif
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