400 lines
9.9 KiB
C
400 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/**
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* Synopsys DesignWare PCIe Endpoint controller driver
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <linux/of.h>
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#include "pcie-designware.h"
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
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{
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struct pci_epc *epc = ep->epc;
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pci_epc_linkup(epc);
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}
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void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
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{
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u32 reg;
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reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writel_dbi2(pci, reg, 0x0);
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dw_pcie_writel_dbi(pci, reg, 0x0);
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dw_pcie_dbi_ro_wr_dis(pci);
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}
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static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
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struct pci_epf_header *hdr)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
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dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
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dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
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dw_pcie_writeb_dbi(pci, PCI_CLASS_PROG, hdr->progif_code);
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dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE,
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hdr->subclass_code | hdr->baseclass_code << 8);
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dw_pcie_writeb_dbi(pci, PCI_CACHE_LINE_SIZE,
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hdr->cache_line_size);
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dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_VENDOR_ID,
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hdr->subsys_vendor_id);
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dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
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dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
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hdr->interrupt_pin);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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}
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static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
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dma_addr_t cpu_addr,
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enum dw_pcie_as_type as_type)
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{
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int ret;
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
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if (free_win >= ep->num_ib_windows) {
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dev_err(pci->dev, "no free inbound window\n");
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return -EINVAL;
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}
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ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
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as_type);
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if (ret < 0) {
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dev_err(pci->dev, "Failed to program IB window\n");
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return ret;
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}
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ep->bar_to_atu[bar] = free_win;
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set_bit(free_win, ep->ib_window_map);
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return 0;
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}
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static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
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u64 pci_addr, size_t size)
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{
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u32 free_win;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
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if (free_win >= ep->num_ob_windows) {
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dev_err(pci->dev, "no free outbound window\n");
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return -EINVAL;
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}
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dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
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phys_addr, pci_addr, size);
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set_bit(free_win, ep->ob_window_map);
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ep->outbound_addr[free_win] = phys_addr;
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return 0;
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}
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static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
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enum pci_barno bar)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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u32 atu_index = ep->bar_to_atu[bar];
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dw_pcie_ep_reset_bar(pci, bar);
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
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clear_bit(atu_index, ep->ib_window_map);
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}
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static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
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enum pci_barno bar,
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dma_addr_t bar_phys, size_t size, int flags)
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{
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int ret;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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enum dw_pcie_as_type as_type;
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u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
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if (!(flags & PCI_BASE_ADDRESS_SPACE))
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as_type = DW_PCIE_AS_MEM;
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else
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as_type = DW_PCIE_AS_IO;
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ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
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if (ret)
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return ret;
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writel_dbi2(pci, reg, size - 1);
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dw_pcie_writel_dbi(pci, reg, flags);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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}
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static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
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u32 *atu_index)
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{
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u32 index;
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for (index = 0; index < ep->num_ob_windows; index++) {
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if (ep->outbound_addr[index] != addr)
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continue;
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*atu_index = index;
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return 0;
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}
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return -EINVAL;
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}
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static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
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phys_addr_t addr)
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{
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int ret;
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u32 atu_index;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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ret = dw_pcie_find_index(ep, addr, &atu_index);
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if (ret < 0)
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return;
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dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
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clear_bit(atu_index, ep->ob_window_map);
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}
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static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
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phys_addr_t addr,
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u64 pci_addr, size_t size)
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{
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int ret;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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ret = dw_pcie_ep_outbound_atu(ep, addr, pci_addr, size);
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if (ret) {
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dev_err(pci->dev, "failed to enable address\n");
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return ret;
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}
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return 0;
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}
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static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
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{
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int val;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
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if (!(val & MSI_CAP_MSI_EN_MASK))
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return -EINVAL;
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val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
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return val;
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}
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static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
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{
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int val;
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
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val &= ~MSI_CAP_MMC_MASK;
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val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
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dw_pcie_dbi_ro_wr_en(pci);
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dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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}
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static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
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enum pci_epc_irq_type type, u8 interrupt_num)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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if (!ep->ops->raise_irq)
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return -EINVAL;
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return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
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}
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static void dw_pcie_ep_stop(struct pci_epc *epc)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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if (!pci->ops->stop_link)
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return;
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pci->ops->stop_link(pci);
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}
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static int dw_pcie_ep_start(struct pci_epc *epc)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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if (!pci->ops->start_link)
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return -EINVAL;
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return pci->ops->start_link(pci);
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}
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static const struct pci_epc_ops epc_ops = {
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.write_header = dw_pcie_ep_write_header,
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.set_bar = dw_pcie_ep_set_bar,
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.clear_bar = dw_pcie_ep_clear_bar,
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.map_addr = dw_pcie_ep_map_addr,
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.unmap_addr = dw_pcie_ep_unmap_addr,
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.set_msi = dw_pcie_ep_set_msi,
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.get_msi = dw_pcie_ep_get_msi,
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.raise_irq = dw_pcie_ep_raise_irq,
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.start = dw_pcie_ep_start,
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.stop = dw_pcie_ep_stop,
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};
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int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
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u8 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct pci_epc *epc = ep->epc;
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u16 msg_ctrl, msg_data;
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u32 msg_addr_lower, msg_addr_upper;
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u64 msg_addr;
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bool has_upper;
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int ret;
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/* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
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msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
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has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
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msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
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if (has_upper) {
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msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
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msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
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} else {
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msg_addr_upper = 0;
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msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
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}
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msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
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ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
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epc->mem->page_size);
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if (ret)
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return ret;
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writel(msg_data | (interrupt_num - 1), ep->msi_mem);
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dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
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return 0;
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}
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void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
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{
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struct pci_epc *epc = ep->epc;
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pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
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epc->mem->page_size);
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pci_epc_mem_exit(epc);
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}
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int dw_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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int ret;
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void *addr;
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struct pci_epc *epc;
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct device *dev = pci->dev;
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struct device_node *np = dev->of_node;
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if (!pci->dbi_base || !pci->dbi_base2) {
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dev_err(dev, "dbi_base/deb_base2 is not populated\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-ib-windows* property\n");
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return ret;
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}
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if (ep->num_ib_windows > MAX_IATU_IN) {
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dev_err(dev, "invalid *num-ib-windows*\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
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if (ret < 0) {
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dev_err(dev, "unable to read *num-ob-windows* property\n");
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return ret;
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}
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if (ep->num_ob_windows > MAX_IATU_OUT) {
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dev_err(dev, "invalid *num-ob-windows*\n");
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return -EINVAL;
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}
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ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
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BITS_TO_LONGS(ep->num_ib_windows),
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GFP_KERNEL);
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if (!ep->ib_window_map)
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return -ENOMEM;
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ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
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BITS_TO_LONGS(ep->num_ob_windows),
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GFP_KERNEL);
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if (!ep->ob_window_map)
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return -ENOMEM;
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addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
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GFP_KERNEL);
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if (!addr)
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return -ENOMEM;
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ep->outbound_addr = addr;
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if (ep->ops->ep_init)
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ep->ops->ep_init(ep);
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epc = devm_pci_epc_create(dev, &epc_ops);
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if (IS_ERR(epc)) {
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dev_err(dev, "failed to create epc device\n");
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return PTR_ERR(epc);
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}
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ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
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if (ret < 0)
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epc->max_functions = 1;
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ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
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ep->page_size);
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if (ret < 0) {
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dev_err(dev, "Failed to initialize address space\n");
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return ret;
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}
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ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
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epc->mem->page_size);
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if (!ep->msi_mem) {
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dev_err(dev, "Failed to reserve memory for MSI\n");
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return -ENOMEM;
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}
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ep->epc = epc;
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epc_set_drvdata(epc, ep);
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dw_pcie_setup(pci);
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return 0;
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}
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