632 lines
13 KiB
C
632 lines
13 KiB
C
/* linux/arch/arm/plat-s3c24xx/devs.c
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*
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Base S3C24XX platform device definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/fb.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/plat-s3c/regs-serial.h>
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#include <asm/plat-s3c24xx/udc.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/plat-s3c24xx/regs-spi.h>
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/* Serial port registrations */
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static struct resource s3c2410_uart0_resource[] = {
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[0] = {
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.start = S3C2410_PA_UART0,
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.end = S3C2410_PA_UART0 + 0x3fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_S3CUART_RX0,
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.end = IRQ_S3CUART_ERR0,
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct resource s3c2410_uart1_resource[] = {
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[0] = {
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.start = S3C2410_PA_UART1,
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.end = S3C2410_PA_UART1 + 0x3fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_S3CUART_RX1,
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.end = IRQ_S3CUART_ERR1,
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct resource s3c2410_uart2_resource[] = {
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[0] = {
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.start = S3C2410_PA_UART2,
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.end = S3C2410_PA_UART2 + 0x3fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_S3CUART_RX2,
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.end = IRQ_S3CUART_ERR2,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
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[0] = {
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.resources = s3c2410_uart0_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
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},
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[1] = {
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.resources = s3c2410_uart1_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
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},
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[2] = {
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.resources = s3c2410_uart2_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
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},
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};
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/* yart devices */
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static struct platform_device s3c24xx_uart_device0 = {
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.id = 0,
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};
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static struct platform_device s3c24xx_uart_device1 = {
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.id = 1,
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};
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static struct platform_device s3c24xx_uart_device2 = {
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.id = 2,
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};
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struct platform_device *s3c24xx_uart_src[3] = {
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&s3c24xx_uart_device0,
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&s3c24xx_uart_device1,
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&s3c24xx_uart_device2,
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};
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struct platform_device *s3c24xx_uart_devs[3] = {
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};
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/* USB Host Controller */
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static struct resource s3c_usb_resource[] = {
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[0] = {
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.start = S3C24XX_PA_USBHOST,
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.end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_USBH,
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.end = IRQ_USBH,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 s3c_device_usb_dmamask = 0xffffffffUL;
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struct platform_device s3c_device_usb = {
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.name = "s3c2410-ohci",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_usb_resource),
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.resource = s3c_usb_resource,
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.dev = {
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.dma_mask = &s3c_device_usb_dmamask,
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.coherent_dma_mask = 0xffffffffUL
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}
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};
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EXPORT_SYMBOL(s3c_device_usb);
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/* LCD Controller */
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static struct resource s3c_lcd_resource[] = {
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[0] = {
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.start = S3C24XX_PA_LCD,
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.end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_LCD,
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.end = IRQ_LCD,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
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struct platform_device s3c_device_lcd = {
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.name = "s3c2410-lcd",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_lcd_resource),
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.resource = s3c_lcd_resource,
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.dev = {
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.dma_mask = &s3c_device_lcd_dmamask,
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.coherent_dma_mask = 0xffffffffUL
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}
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};
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EXPORT_SYMBOL(s3c_device_lcd);
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void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
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{
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struct s3c2410fb_mach_info *npd;
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npd = kmalloc(sizeof(*npd), GFP_KERNEL);
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if (npd) {
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memcpy(npd, pd, sizeof(*npd));
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s3c_device_lcd.dev.platform_data = npd;
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} else {
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printk(KERN_ERR "no memory for LCD platform data\n");
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}
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}
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/* NAND Controller */
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static struct resource s3c_nand_resource[] = {
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[0] = {
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.start = S3C2410_PA_NAND,
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.end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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struct platform_device s3c_device_nand = {
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.name = "s3c2410-nand",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_nand_resource),
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.resource = s3c_nand_resource,
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};
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EXPORT_SYMBOL(s3c_device_nand);
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/* USB Device (Gadget)*/
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static struct resource s3c_usbgadget_resource[] = {
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[0] = {
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.start = S3C24XX_PA_USBDEV,
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.end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_USBD,
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.end = IRQ_USBD,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device s3c_device_usbgadget = {
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.name = "s3c2410-usbgadget",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
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.resource = s3c_usbgadget_resource,
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};
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EXPORT_SYMBOL(s3c_device_usbgadget);
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void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
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{
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struct s3c2410_udc_mach_info *npd;
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npd = kmalloc(sizeof(*npd), GFP_KERNEL);
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if (npd) {
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memcpy(npd, pd, sizeof(*npd));
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s3c_device_usbgadget.dev.platform_data = npd;
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} else {
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printk(KERN_ERR "no memory for udc platform data\n");
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}
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}
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/* Watchdog */
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static struct resource s3c_wdt_resource[] = {
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[0] = {
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.start = S3C24XX_PA_WATCHDOG,
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.end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_WDT,
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.end = IRQ_WDT,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device s3c_device_wdt = {
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.name = "s3c2410-wdt",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_wdt_resource),
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.resource = s3c_wdt_resource,
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};
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EXPORT_SYMBOL(s3c_device_wdt);
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/* I2C */
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static struct resource s3c_i2c_resource[] = {
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[0] = {
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.start = S3C24XX_PA_IIC,
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.end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IIC,
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.end = IRQ_IIC,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device s3c_device_i2c = {
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.name = "s3c2410-i2c",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_i2c_resource),
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.resource = s3c_i2c_resource,
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};
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EXPORT_SYMBOL(s3c_device_i2c);
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/* IIS */
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static struct resource s3c_iis_resource[] = {
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[0] = {
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.start = S3C24XX_PA_IIS,
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.end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
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.flags = IORESOURCE_MEM,
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}
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};
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static u64 s3c_device_iis_dmamask = 0xffffffffUL;
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struct platform_device s3c_device_iis = {
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.name = "s3c2410-iis",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_iis_resource),
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.resource = s3c_iis_resource,
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.dev = {
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.dma_mask = &s3c_device_iis_dmamask,
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.coherent_dma_mask = 0xffffffffUL
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}
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};
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EXPORT_SYMBOL(s3c_device_iis);
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/* RTC */
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static struct resource s3c_rtc_resource[] = {
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[0] = {
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.start = S3C24XX_PA_RTC,
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.end = S3C24XX_PA_RTC + 0xff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_RTC,
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.end = IRQ_RTC,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = IRQ_TICK,
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.end = IRQ_TICK,
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.flags = IORESOURCE_IRQ
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}
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};
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struct platform_device s3c_device_rtc = {
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.name = "s3c2410-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_rtc_resource),
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.resource = s3c_rtc_resource,
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};
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EXPORT_SYMBOL(s3c_device_rtc);
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/* ADC */
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static struct resource s3c_adc_resource[] = {
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[0] = {
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.start = S3C24XX_PA_ADC,
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.end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_TC,
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.end = IRQ_TC,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = IRQ_ADC,
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.end = IRQ_ADC,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device s3c_device_adc = {
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.name = "s3c2410-adc",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_adc_resource),
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.resource = s3c_adc_resource,
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};
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/* SDI */
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static struct resource s3c_sdi_resource[] = {
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[0] = {
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.start = S3C2410_PA_SDI,
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.end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SDI,
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.end = IRQ_SDI,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device s3c_device_sdi = {
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.name = "s3c2410-sdi",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_sdi_resource),
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.resource = s3c_sdi_resource,
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};
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EXPORT_SYMBOL(s3c_device_sdi);
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/* High-speed MMC/SD */
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static struct resource s3c_hsmmc_resource[] = {
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[0] = {
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.start = S3C2443_PA_HSMMC,
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.end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_S3C2443_HSMMC,
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.end = IRQ_S3C2443_HSMMC,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
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struct platform_device s3c_device_hsmmc = {
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.name = "s3c-sdhci",
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.id = -1,
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.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
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.resource = s3c_hsmmc_resource,
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.dev = {
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.dma_mask = &s3c_device_hsmmc_dmamask,
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.coherent_dma_mask = 0xffffffffUL
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}
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};
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/* SPI (0) */
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static struct resource s3c_spi0_resource[] = {
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[0] = {
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.start = S3C24XX_PA_SPI,
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.end = S3C24XX_PA_SPI + 0x1f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SPI0,
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.end = IRQ_SPI0,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
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struct platform_device s3c_device_spi0 = {
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.name = "s3c2410-spi",
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.id = 0,
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.num_resources = ARRAY_SIZE(s3c_spi0_resource),
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.resource = s3c_spi0_resource,
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.dev = {
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.dma_mask = &s3c_device_spi0_dmamask,
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.coherent_dma_mask = 0xffffffffUL
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}
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};
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EXPORT_SYMBOL(s3c_device_spi0);
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/* SPI (1) */
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static struct resource s3c_spi1_resource[] = {
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[0] = {
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.start = S3C24XX_PA_SPI + S3C2410_SPI1,
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.end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SPI1,
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.end = IRQ_SPI1,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
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struct platform_device s3c_device_spi1 = {
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.name = "s3c2410-spi",
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.id = 1,
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.num_resources = ARRAY_SIZE(s3c_spi1_resource),
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.resource = s3c_spi1_resource,
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.dev = {
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.dma_mask = &s3c_device_spi1_dmamask,
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.coherent_dma_mask = 0xffffffffUL
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}
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};
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EXPORT_SYMBOL(s3c_device_spi1);
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/* pwm timer blocks */
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static struct resource s3c_timer0_resource[] = {
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[0] = {
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.start = S3C24XX_PA_TIMER + 0x0C,
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.end = S3C24XX_PA_TIMER + 0x0C + 0xB,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_TIMER0,
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.end = IRQ_TIMER0,
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.flags = IORESOURCE_IRQ,
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}
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};
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struct platform_device s3c_device_timer0 = {
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.name = "s3c2410-timer",
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.id = 0,
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.num_resources = ARRAY_SIZE(s3c_timer0_resource),
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.resource = s3c_timer0_resource,
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};
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EXPORT_SYMBOL(s3c_device_timer0);
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|
/* timer 1 */
|
|
|
|
static struct resource s3c_timer1_resource[] = {
|
|
[0] = {
|
|
.start = S3C24XX_PA_TIMER + 0x18,
|
|
.end = S3C24XX_PA_TIMER + 0x23,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = IRQ_TIMER1,
|
|
.end = IRQ_TIMER1,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
|
|
};
|
|
|
|
struct platform_device s3c_device_timer1 = {
|
|
.name = "s3c2410-timer",
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(s3c_timer1_resource),
|
|
.resource = s3c_timer1_resource,
|
|
};
|
|
|
|
EXPORT_SYMBOL(s3c_device_timer1);
|
|
|
|
/* timer 2 */
|
|
|
|
static struct resource s3c_timer2_resource[] = {
|
|
[0] = {
|
|
.start = S3C24XX_PA_TIMER + 0x24,
|
|
.end = S3C24XX_PA_TIMER + 0x2F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = IRQ_TIMER2,
|
|
.end = IRQ_TIMER2,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
|
|
};
|
|
|
|
struct platform_device s3c_device_timer2 = {
|
|
.name = "s3c2410-timer",
|
|
.id = 2,
|
|
.num_resources = ARRAY_SIZE(s3c_timer2_resource),
|
|
.resource = s3c_timer2_resource,
|
|
};
|
|
|
|
EXPORT_SYMBOL(s3c_device_timer2);
|
|
|
|
/* timer 3 */
|
|
|
|
static struct resource s3c_timer3_resource[] = {
|
|
[0] = {
|
|
.start = S3C24XX_PA_TIMER + 0x30,
|
|
.end = S3C24XX_PA_TIMER + 0x3B,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = IRQ_TIMER3,
|
|
.end = IRQ_TIMER3,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
|
|
};
|
|
|
|
struct platform_device s3c_device_timer3 = {
|
|
.name = "s3c2410-timer",
|
|
.id = 3,
|
|
.num_resources = ARRAY_SIZE(s3c_timer3_resource),
|
|
.resource = s3c_timer3_resource,
|
|
};
|
|
|
|
EXPORT_SYMBOL(s3c_device_timer3);
|
|
|
|
#ifdef CONFIG_CPU_S3C2440
|
|
|
|
/* Camif Controller */
|
|
|
|
static struct resource s3c_camif_resource[] = {
|
|
[0] = {
|
|
.start = S3C2440_PA_CAMIF,
|
|
.end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = IRQ_CAM,
|
|
.end = IRQ_CAM,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
|
|
};
|
|
|
|
static u64 s3c_device_camif_dmamask = 0xffffffffUL;
|
|
|
|
struct platform_device s3c_device_camif = {
|
|
.name = "s3c2440-camif",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(s3c_camif_resource),
|
|
.resource = s3c_camif_resource,
|
|
.dev = {
|
|
.dma_mask = &s3c_device_camif_dmamask,
|
|
.coherent_dma_mask = 0xffffffffUL
|
|
}
|
|
};
|
|
|
|
EXPORT_SYMBOL(s3c_device_camif);
|
|
|
|
#endif // CONFIG_CPU_S32440
|