495 lines
12 KiB
C
495 lines
12 KiB
C
/*
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* Copyright 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regulator/consumer.h>
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#include <linux/irqchip/arm-gic.h>
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#include "common.h"
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#include "hardware.h"
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#define GPC_CNTR 0x000
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#define GPC_IMR1 0x008
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#define GPC_PGC_GPU_PDN 0x260
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#define GPC_PGC_GPU_PUPSCR 0x264
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#define GPC_PGC_GPU_PDNSCR 0x268
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#define GPC_PGC_CPU_PDN 0x2a0
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#define GPC_PGC_CPU_PUPSCR 0x2a4
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#define GPC_PGC_CPU_PDNSCR 0x2a8
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#define GPC_PGC_SW2ISO_SHIFT 0x8
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#define GPC_PGC_SW_SHIFT 0x0
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#define IMR_NUM 4
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#define GPC_MAX_IRQS (IMR_NUM * 32)
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#define GPU_VPU_PUP_REQ BIT(1)
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#define GPU_VPU_PDN_REQ BIT(0)
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#define GPC_CLK_MAX 6
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struct pu_domain {
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struct generic_pm_domain base;
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struct regulator *reg;
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struct clk *clk[GPC_CLK_MAX];
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int num_clks;
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};
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static void __iomem *gpc_base;
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static u32 gpc_wake_irqs[IMR_NUM];
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static u32 gpc_saved_imrs[IMR_NUM];
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void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
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{
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writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
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(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
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}
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void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
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{
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writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
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(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
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}
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void imx_gpc_set_arm_power_in_lpm(bool power_off)
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{
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writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
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}
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void imx_gpc_pre_suspend(bool arm_power_off)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* Tell GPC to power off ARM core when suspend */
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if (arm_power_off)
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imx_gpc_set_arm_power_in_lpm(arm_power_off);
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
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}
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}
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void imx_gpc_post_resume(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* Keep ARM core powered on for other low-power modes */
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imx_gpc_set_arm_power_in_lpm(false);
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned int idx = d->hwirq / 32;
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u32 mask;
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mask = 1 << d->hwirq % 32;
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gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
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gpc_wake_irqs[idx] & ~mask;
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/*
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* Do *not* call into the parent, as the GIC doesn't have any
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* wake-up facility...
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*/
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return 0;
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}
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void imx_gpc_mask_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~0, reg_imr1 + i * 4);
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}
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}
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void imx_gpc_restore_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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void imx_gpc_hwirq_unmask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val &= ~(1 << hwirq % 32);
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writel_relaxed(val, reg);
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}
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void imx_gpc_hwirq_mask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val |= 1 << (hwirq % 32);
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writel_relaxed(val, reg);
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}
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static void imx_gpc_irq_unmask(struct irq_data *d)
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{
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imx_gpc_hwirq_unmask(d->hwirq);
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irq_chip_unmask_parent(d);
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}
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static void imx_gpc_irq_mask(struct irq_data *d)
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{
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imx_gpc_hwirq_mask(d->hwirq);
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irq_chip_mask_parent(d);
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}
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static struct irq_chip imx_gpc_chip = {
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.name = "GPC",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = imx_gpc_irq_mask,
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.irq_unmask = imx_gpc_irq_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = imx_gpc_irq_set_wake,
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.irq_set_type = irq_chip_set_type_parent,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int imx_gpc_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int imx_gpc_domain_alloc(struct irq_domain *domain,
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unsigned int irq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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if (hwirq >= GPC_MAX_IRQS)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
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&imx_gpc_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops imx_gpc_domain_ops = {
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.translate = imx_gpc_domain_translate,
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.alloc = imx_gpc_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init imx_gpc_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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int i;
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if (!parent) {
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pr_err("%s: no parent, giving up\n", node->full_name);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%s: unable to obtain parent domain\n", node->full_name);
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return -ENXIO;
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}
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gpc_base = of_iomap(node, 0);
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if (WARN_ON(!gpc_base))
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return -ENOMEM;
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domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
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node, &imx_gpc_domain_ops,
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NULL);
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if (!domain) {
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iounmap(gpc_base);
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return -ENOMEM;
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}
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/* Initially mask all interrupts */
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
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/*
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* Clear the OF_POPULATED flag set in of_irq_init so that
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* later the GPC power domain driver will not be skipped.
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*/
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of_node_clear_flag(node, OF_POPULATED);
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return 0;
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}
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IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
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void __init imx_gpc_check_dt(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
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if (WARN_ON(!np))
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return;
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if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
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pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
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/* map GPC, so that at least CPUidle and WARs keep working */
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gpc_base = of_iomap(np, 0);
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}
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}
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static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
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{
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int iso, iso2sw;
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u32 val;
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/* Read ISO and ISO2SW power down delays */
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val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
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iso = val & 0x3f;
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iso2sw = (val >> 8) & 0x3f;
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/* Gate off PU domain when GPU/VPU when powered down */
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writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
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/* Request GPC to power down GPU/VPU */
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val = readl_relaxed(gpc_base + GPC_CNTR);
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val |= GPU_VPU_PDN_REQ;
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writel_relaxed(val, gpc_base + GPC_CNTR);
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/* Wait ISO + ISO2SW IPG clock cycles */
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ndelay((iso + iso2sw) * 1000 / 66);
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}
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static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
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{
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struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
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_imx6q_pm_pu_power_off(genpd);
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if (pu->reg)
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regulator_disable(pu->reg);
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return 0;
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}
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static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
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{
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struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
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int i, ret, sw, sw2iso;
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u32 val;
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if (pu->reg)
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ret = regulator_enable(pu->reg);
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if (pu->reg && ret) {
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pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
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return ret;
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}
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/* Enable reset clocks for all devices in the PU domain */
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for (i = 0; i < pu->num_clks; i++)
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clk_prepare_enable(pu->clk[i]);
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/* Gate off PU domain when GPU/VPU when powered down */
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writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
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/* Read ISO and ISO2SW power down delays */
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val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
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sw = val & 0x3f;
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sw2iso = (val >> 8) & 0x3f;
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/* Request GPC to power up GPU/VPU */
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val = readl_relaxed(gpc_base + GPC_CNTR);
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val |= GPU_VPU_PUP_REQ;
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writel_relaxed(val, gpc_base + GPC_CNTR);
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/* Wait ISO + ISO2SW IPG clock cycles */
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ndelay((sw + sw2iso) * 1000 / 66);
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/* Disable reset clocks for all devices in the PU domain */
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for (i = 0; i < pu->num_clks; i++)
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clk_disable_unprepare(pu->clk[i]);
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return 0;
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}
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static struct generic_pm_domain imx6q_arm_domain = {
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.name = "ARM",
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};
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static struct pu_domain imx6q_pu_domain = {
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.base = {
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.name = "PU",
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.power_off = imx6q_pm_pu_power_off,
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.power_on = imx6q_pm_pu_power_on,
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},
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};
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static struct generic_pm_domain imx6sl_display_domain = {
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.name = "DISPLAY",
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};
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static struct generic_pm_domain *imx_gpc_domains[] = {
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&imx6q_arm_domain,
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&imx6q_pu_domain.base,
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&imx6sl_display_domain,
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};
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static struct genpd_onecell_data imx_gpc_onecell_data = {
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.domains = imx_gpc_domains,
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.num_domains = ARRAY_SIZE(imx_gpc_domains),
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};
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static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
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{
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struct clk *clk;
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int i, ret;
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imx6q_pu_domain.reg = pu_reg;
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for (i = 0; ; i++) {
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clk = of_clk_get(dev->of_node, i);
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if (IS_ERR(clk))
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break;
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if (i >= GPC_CLK_MAX) {
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dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
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goto clk_err;
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}
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imx6q_pu_domain.clk[i] = clk;
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}
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imx6q_pu_domain.num_clks = i;
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/* Enable power always in case bootloader disabled it. */
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imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
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if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
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return 0;
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imx6q_pu_domain.base.states = devm_kzalloc(dev,
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sizeof(*imx6q_pu_domain.base.states),
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GFP_KERNEL);
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if (!imx6q_pu_domain.base.states)
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return -ENOMEM;
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imx6q_pu_domain.base.states[0].power_off_latency_ns = 25000;
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imx6q_pu_domain.base.states[0].power_on_latency_ns = 2000000;
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imx6q_pu_domain.base.state_count = 1;
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for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
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pm_genpd_init(imx_gpc_domains[i], NULL, false);
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ret = of_genpd_add_provider_onecell(dev->of_node,
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&imx_gpc_onecell_data);
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if (ret)
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goto power_off;
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return 0;
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power_off:
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imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
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clk_err:
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while (i--)
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clk_put(imx6q_pu_domain.clk[i]);
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imx6q_pu_domain.reg = NULL;
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return -EINVAL;
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}
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static int imx_gpc_probe(struct platform_device *pdev)
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{
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struct regulator *pu_reg;
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int ret;
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/* bail out if DT too old and doesn't provide the necessary info */
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if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
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return 0;
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pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
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if (PTR_ERR(pu_reg) == -ENODEV)
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pu_reg = NULL;
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if (IS_ERR(pu_reg)) {
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ret = PTR_ERR(pu_reg);
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dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
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return ret;
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}
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return imx_gpc_genpd_init(&pdev->dev, pu_reg);
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}
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static const struct of_device_id imx_gpc_dt_ids[] = {
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{ .compatible = "fsl,imx6q-gpc" },
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{ .compatible = "fsl,imx6sl-gpc" },
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{ }
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};
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static struct platform_driver imx_gpc_driver = {
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.driver = {
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.name = "imx-gpc",
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.of_match_table = imx_gpc_dt_ids,
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},
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.probe = imx_gpc_probe,
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};
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static int __init imx_pgc_init(void)
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{
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return platform_driver_register(&imx_gpc_driver);
|
|
}
|
|
subsys_initcall(imx_pgc_init);
|