778 lines
18 KiB
C
778 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMx3 Wkup M3 IPC driver
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*
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* Copyright (C) 2015 Texas Instruments, Inc.
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*
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* Dave Gerlach <d-gerlach@ti.com>
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*/
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#include <linux/debugfs.h>
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#include <linux/err.h>
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#include <linux/firmware.h>
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#include <linux/kernel.h>
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#include <linux/kthread.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/omap-mailbox.h>
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#include <linux/platform_device.h>
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#include <linux/remoteproc.h>
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#include <linux/suspend.h>
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#include <linux/wkup_m3_ipc.h>
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#define AM33XX_CTRL_IPC_REG_COUNT 0x8
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#define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m))
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/* AM33XX M3_TXEV_EOI register */
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#define AM33XX_CONTROL_M3_TXEV_EOI 0x00
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#define AM33XX_M3_TXEV_ACK (0x1 << 0)
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#define AM33XX_M3_TXEV_ENABLE (0x0 << 0)
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#define IPC_CMD_DS0 0x4
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#define IPC_CMD_STANDBY 0xc
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#define IPC_CMD_IDLE 0x10
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#define IPC_CMD_RESET 0xe
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#define DS_IPC_DEFAULT 0xffffffff
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#define M3_VERSION_UNKNOWN 0x0000ffff
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#define M3_BASELINE_VERSION 0x191
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#define M3_STATUS_RESP_MASK (0xffff << 16)
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#define M3_FW_VERSION_MASK 0xffff
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#define M3_WAKE_SRC_MASK 0xff
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#define IPC_MEM_TYPE_SHIFT (0x0)
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#define IPC_MEM_TYPE_MASK (0x7 << 0)
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#define IPC_VTT_STAT_SHIFT (0x3)
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#define IPC_VTT_STAT_MASK (0x1 << 3)
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#define IPC_VTT_GPIO_PIN_SHIFT (0x4)
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#define IPC_VTT_GPIO_PIN_MASK (0x3f << 4)
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#define IPC_IO_ISOLATION_STAT_SHIFT (10)
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#define IPC_IO_ISOLATION_STAT_MASK (0x1 << 10)
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#define IPC_DBG_HALT_SHIFT (11)
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#define IPC_DBG_HALT_MASK (0x1 << 11)
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#define M3_STATE_UNKNOWN 0
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#define M3_STATE_RESET 1
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#define M3_STATE_INITED 2
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#define M3_STATE_MSG_FOR_LP 3
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#define M3_STATE_MSG_FOR_RESET 4
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#define WKUP_M3_SD_FW_MAGIC 0x570C
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#define WKUP_M3_DMEM_START 0x80000
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#define WKUP_M3_AUXDATA_OFFSET 0x1000
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#define WKUP_M3_AUXDATA_SIZE 0xFF
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static struct wkup_m3_ipc *m3_ipc_state;
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static const struct wkup_m3_wakeup_src wakeups[] = {
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{.irq_nr = 16, .src = "PRCM"},
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{.irq_nr = 35, .src = "USB0_PHY"},
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{.irq_nr = 36, .src = "USB1_PHY"},
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{.irq_nr = 40, .src = "I2C0"},
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{.irq_nr = 41, .src = "RTC Timer"},
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{.irq_nr = 42, .src = "RTC Alarm"},
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{.irq_nr = 43, .src = "Timer0"},
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{.irq_nr = 44, .src = "Timer1"},
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{.irq_nr = 45, .src = "UART"},
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{.irq_nr = 46, .src = "GPIO0"},
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{.irq_nr = 48, .src = "MPU_WAKE"},
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{.irq_nr = 49, .src = "WDT0"},
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{.irq_nr = 50, .src = "WDT1"},
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{.irq_nr = 51, .src = "ADC_TSC"},
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{.irq_nr = 0, .src = "Unknown"},
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};
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/**
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* wkup_m3_copy_aux_data - Copy auxiliary data to special region of m3 dmem
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* @data - pointer to data
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* @sz - size of data to copy (limit 256 bytes)
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*
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* Copies any additional blob of data to the wkup_m3 dmem to be used by the
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* firmware
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*/
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static unsigned long wkup_m3_copy_aux_data(struct wkup_m3_ipc *m3_ipc,
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const void *data, int sz)
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{
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unsigned long aux_data_dev_addr;
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void *aux_data_addr;
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aux_data_dev_addr = WKUP_M3_DMEM_START + WKUP_M3_AUXDATA_OFFSET;
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aux_data_addr = rproc_da_to_va(m3_ipc->rproc,
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aux_data_dev_addr,
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WKUP_M3_AUXDATA_SIZE,
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NULL);
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memcpy(aux_data_addr, data, sz);
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return WKUP_M3_AUXDATA_OFFSET;
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}
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static void wkup_m3_scale_data_fw_cb(const struct firmware *fw, void *context)
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{
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unsigned long val, aux_base;
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struct wkup_m3_scale_data_header hdr;
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struct wkup_m3_ipc *m3_ipc = context;
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struct device *dev = m3_ipc->dev;
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if (!fw) {
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dev_err(dev, "Voltage scale fw name given but file missing.\n");
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return;
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}
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memcpy(&hdr, fw->data, sizeof(hdr));
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if (hdr.magic != WKUP_M3_SD_FW_MAGIC) {
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dev_err(dev, "PM: Voltage Scale Data binary does not appear valid.\n");
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goto release_sd_fw;
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}
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aux_base = wkup_m3_copy_aux_data(m3_ipc, fw->data + sizeof(hdr),
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fw->size - sizeof(hdr));
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val = (aux_base + hdr.sleep_offset);
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val |= ((aux_base + hdr.wake_offset) << 16);
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m3_ipc->volt_scale_offsets = val;
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release_sd_fw:
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release_firmware(fw);
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};
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static int wkup_m3_init_scale_data(struct wkup_m3_ipc *m3_ipc,
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struct device *dev)
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{
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int ret = 0;
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/*
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* If no name is provided, user has already been warned, pm will
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* still work so return 0
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*/
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if (!m3_ipc->sd_fw_name)
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return ret;
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ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
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m3_ipc->sd_fw_name, dev, GFP_ATOMIC,
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m3_ipc, wkup_m3_scale_data_fw_cb);
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return ret;
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}
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#ifdef CONFIG_DEBUG_FS
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static void wkup_m3_set_halt_late(bool enabled)
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{
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if (enabled)
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m3_ipc_state->halt = (1 << IPC_DBG_HALT_SHIFT);
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else
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m3_ipc_state->halt = 0;
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}
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static int option_get(void *data, u64 *val)
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{
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u32 *option = data;
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*val = *option;
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return 0;
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}
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static int option_set(void *data, u64 val)
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{
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u32 *option = data;
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*option = val;
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if (option == &m3_ipc_state->halt) {
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if (val)
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wkup_m3_set_halt_late(true);
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else
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wkup_m3_set_halt_late(false);
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}
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(wkup_m3_ipc_option_fops, option_get, option_set,
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"%llu\n");
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static int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc)
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{
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m3_ipc->dbg_path = debugfs_create_dir("wkup_m3_ipc", NULL);
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if (!m3_ipc->dbg_path)
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return -EINVAL;
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(void)debugfs_create_file("enable_late_halt", 0644,
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m3_ipc->dbg_path,
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&m3_ipc->halt,
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&wkup_m3_ipc_option_fops);
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return 0;
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}
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static inline void wkup_m3_ipc_dbg_destroy(struct wkup_m3_ipc *m3_ipc)
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{
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debugfs_remove_recursive(m3_ipc->dbg_path);
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}
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#else
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static inline int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc)
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{
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return 0;
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}
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static inline void wkup_m3_ipc_dbg_destroy(struct wkup_m3_ipc *m3_ipc)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
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{
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writel(AM33XX_M3_TXEV_ACK,
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m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
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}
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static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
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{
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writel(AM33XX_M3_TXEV_ENABLE,
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m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
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}
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static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
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u32 val, int ipc_reg_num)
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{
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if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
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"ipc register operation out of range"))
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return;
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writel(val, m3_ipc->ipc_mem_base +
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AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
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}
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static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
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int ipc_reg_num)
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{
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if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
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"ipc register operation out of range"))
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return 0;
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return readl(m3_ipc->ipc_mem_base +
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AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
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}
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static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
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{
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int val;
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val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
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return val & M3_FW_VERSION_MASK;
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}
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static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
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{
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struct wkup_m3_ipc *m3_ipc = ipc_data;
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struct device *dev = m3_ipc->dev;
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int ver = 0;
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am33xx_txev_eoi(m3_ipc);
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switch (m3_ipc->state) {
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case M3_STATE_RESET:
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ver = wkup_m3_fw_version_read(m3_ipc);
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if (ver == M3_VERSION_UNKNOWN ||
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ver < M3_BASELINE_VERSION) {
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dev_warn(dev, "CM3 Firmware Version %x not supported\n",
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ver);
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} else {
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dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
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}
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m3_ipc->state = M3_STATE_INITED;
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wkup_m3_init_scale_data(m3_ipc, dev);
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complete(&m3_ipc->sync_complete);
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break;
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case M3_STATE_MSG_FOR_RESET:
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m3_ipc->state = M3_STATE_INITED;
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complete(&m3_ipc->sync_complete);
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break;
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case M3_STATE_MSG_FOR_LP:
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complete(&m3_ipc->sync_complete);
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break;
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case M3_STATE_UNKNOWN:
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dev_warn(dev, "Unknown CM3 State\n");
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}
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am33xx_txev_enable(m3_ipc);
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return IRQ_HANDLED;
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}
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static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
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{
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struct device *dev = m3_ipc->dev;
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mbox_msg_t dummy_msg = 0;
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int ret;
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if (!m3_ipc->mbox) {
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dev_err(dev,
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"No IPC channel to communicate with wkup_m3!\n");
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return -EIO;
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}
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/*
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* Write a dummy message to the mailbox in order to trigger the RX
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* interrupt to alert the M3 that data is available in the IPC
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* registers. We must enable the IRQ here and disable it after in
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* the RX callback to avoid multiple interrupts being received
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* by the CM3.
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*/
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ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
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if (ret < 0) {
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dev_err(dev, "%s: mbox_send_message() failed: %d\n",
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__func__, ret);
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return ret;
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}
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ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
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msecs_to_jiffies(500));
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if (!ret) {
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dev_err(dev, "MPU<->CM3 sync failure\n");
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m3_ipc->state = M3_STATE_UNKNOWN;
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return -EIO;
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}
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mbox_client_txdone(m3_ipc->mbox, 0);
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return 0;
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}
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static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
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{
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struct device *dev = m3_ipc->dev;
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mbox_msg_t dummy_msg = 0;
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int ret;
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if (!m3_ipc->mbox) {
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dev_err(dev,
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"No IPC channel to communicate with wkup_m3!\n");
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return -EIO;
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}
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ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
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if (ret < 0) {
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dev_err(dev, "%s: mbox_send_message() failed: %d\n",
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__func__, ret);
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return ret;
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}
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mbox_client_txdone(m3_ipc->mbox, 0);
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return 0;
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}
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static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
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{
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return ((m3_ipc->state != M3_STATE_RESET) &&
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(m3_ipc->state != M3_STATE_UNKNOWN));
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}
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static void wkup_m3_set_vtt_gpio(struct wkup_m3_ipc *m3_ipc, int gpio)
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{
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m3_ipc->vtt_conf = (1 << IPC_VTT_STAT_SHIFT) |
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(gpio << IPC_VTT_GPIO_PIN_SHIFT);
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}
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static void wkup_m3_set_io_isolation(struct wkup_m3_ipc *m3_ipc)
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{
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m3_ipc->isolation_conf = (1 << IPC_IO_ISOLATION_STAT_SHIFT);
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}
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/* Public functions */
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/**
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* wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
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* @m3_ipc: Pointer to wkup_m3_ipc context
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* @mem_type: memory type value read directly from emif
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*
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* wkup_m3 must know what memory type is in use to properly suspend
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* and resume.
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*/
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static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
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{
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m3_ipc->mem_type = mem_type;
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}
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/**
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* wkup_m3_set_resume_address - Pass wkup_m3 resume address
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* @m3_ipc: Pointer to wkup_m3_ipc context
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* @addr: Physical address from which resume code should execute
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*/
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static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
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{
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m3_ipc->resume_addr = (unsigned long)addr;
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}
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/**
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* wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
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* @m3_ipc: Pointer to wkup_m3_ipc context
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*
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* Returns code representing the status of a low power mode transition.
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* 0 - Successful transition
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* 1 - Failure to transition to low power state
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*/
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static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
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{
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unsigned int i;
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int val;
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val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
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i = M3_STATUS_RESP_MASK & val;
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i >>= __ffs(M3_STATUS_RESP_MASK);
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return i;
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}
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/**
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* wkup_m3_prepare_low_power - Request preparation for transition to
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* low power state
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* @m3_ipc: Pointer to wkup_m3_ipc context
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* @state: A kernel suspend state to enter, either MEM or STANDBY
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*
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* Returns 0 if preparation was successful, otherwise returns error code
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*/
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static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
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{
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struct device *dev = m3_ipc->dev;
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int m3_power_state;
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int ret = 0;
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if (!wkup_m3_is_available(m3_ipc))
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return -ENODEV;
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switch (state) {
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case WKUP_M3_DEEPSLEEP:
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m3_power_state = IPC_CMD_DS0;
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wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->volt_scale_offsets, 5);
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break;
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case WKUP_M3_STANDBY:
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m3_power_state = IPC_CMD_STANDBY;
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
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break;
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case WKUP_M3_IDLE:
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m3_power_state = IPC_CMD_IDLE;
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wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
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break;
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default:
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return 1;
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}
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/* Program each required IPC register then write defaults to others */
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wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
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wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
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wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type |
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m3_ipc->vtt_conf |
|
|
m3_ipc->isolation_conf |
|
|
m3_ipc->halt, 4);
|
|
|
|
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
|
|
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
|
|
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
|
|
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
|
|
|
|
m3_ipc->state = M3_STATE_MSG_FOR_LP;
|
|
|
|
if (state == WKUP_M3_IDLE)
|
|
ret = wkup_m3_ping_noirq(m3_ipc);
|
|
else
|
|
ret = wkup_m3_ping(m3_ipc);
|
|
|
|
if (ret) {
|
|
dev_err(dev, "Unable to ping CM3\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* wkup_m3_finish_low_power - Return m3 to reset state
|
|
* @m3_ipc: Pointer to wkup_m3_ipc context
|
|
*
|
|
* Returns 0 if reset was successful, otherwise returns error code
|
|
*/
|
|
static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
|
|
{
|
|
struct device *dev = m3_ipc->dev;
|
|
int ret = 0;
|
|
|
|
if (!wkup_m3_is_available(m3_ipc))
|
|
return -ENODEV;
|
|
|
|
wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
|
|
wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
|
|
|
|
m3_ipc->state = M3_STATE_MSG_FOR_RESET;
|
|
|
|
ret = wkup_m3_ping(m3_ipc);
|
|
if (ret) {
|
|
dev_err(dev, "Unable to ping CM3\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
|
|
* @m3_ipc: Pointer to wkup_m3_ipc context
|
|
*/
|
|
static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
|
|
{
|
|
unsigned int wakeup_src_idx;
|
|
int j, val;
|
|
|
|
val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
|
|
|
|
wakeup_src_idx = val & M3_WAKE_SRC_MASK;
|
|
|
|
for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
|
|
if (wakeups[j].irq_nr == wakeup_src_idx)
|
|
return wakeups[j].src;
|
|
}
|
|
return wakeups[j].src;
|
|
}
|
|
|
|
/**
|
|
* wkup_m3_set_rtc_only - Set the rtc_only flag
|
|
* @m3_ipc: Pointer to wkup_m3_ipc context
|
|
*/
|
|
static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
|
|
{
|
|
if (m3_ipc_state)
|
|
m3_ipc_state->is_rtc_only = true;
|
|
}
|
|
|
|
static struct wkup_m3_ipc_ops ipc_ops = {
|
|
.set_mem_type = wkup_m3_set_mem_type,
|
|
.set_resume_address = wkup_m3_set_resume_address,
|
|
.prepare_low_power = wkup_m3_prepare_low_power,
|
|
.finish_low_power = wkup_m3_finish_low_power,
|
|
.request_pm_status = wkup_m3_request_pm_status,
|
|
.request_wake_src = wkup_m3_request_wake_src,
|
|
.set_rtc_only = wkup_m3_set_rtc_only,
|
|
};
|
|
|
|
/**
|
|
* wkup_m3_ipc_get - Return handle to wkup_m3_ipc
|
|
*
|
|
* Returns NULL if the wkup_m3 is not yet available, otherwise returns
|
|
* pointer to wkup_m3_ipc struct.
|
|
*/
|
|
struct wkup_m3_ipc *wkup_m3_ipc_get(void)
|
|
{
|
|
if (m3_ipc_state)
|
|
get_device(m3_ipc_state->dev);
|
|
else
|
|
return NULL;
|
|
|
|
return m3_ipc_state;
|
|
}
|
|
EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
|
|
|
|
/**
|
|
* wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
|
|
* @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
|
|
*/
|
|
void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
|
|
{
|
|
if (m3_ipc_state)
|
|
put_device(m3_ipc_state->dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
|
|
|
|
static int wkup_m3_rproc_boot_thread(void *arg)
|
|
{
|
|
struct wkup_m3_ipc *m3_ipc = arg;
|
|
struct device *dev = m3_ipc->dev;
|
|
int ret;
|
|
|
|
init_completion(&m3_ipc->sync_complete);
|
|
|
|
ret = rproc_boot(m3_ipc->rproc);
|
|
if (ret)
|
|
dev_err(dev, "rproc_boot failed\n");
|
|
else
|
|
m3_ipc_state = m3_ipc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wkup_m3_ipc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
int irq, ret, temp;
|
|
phandle rproc_phandle;
|
|
struct rproc *m3_rproc;
|
|
struct resource *res;
|
|
struct task_struct *task;
|
|
struct wkup_m3_ipc *m3_ipc;
|
|
struct device_node *np = dev->of_node;
|
|
|
|
m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
|
|
if (!m3_ipc)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(m3_ipc->ipc_mem_base))
|
|
return PTR_ERR(m3_ipc->ipc_mem_base);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
|
|
0, "wkup_m3_txev", m3_ipc);
|
|
if (ret) {
|
|
dev_err(dev, "request_irq failed\n");
|
|
return ret;
|
|
}
|
|
|
|
m3_ipc->mbox_client.dev = dev;
|
|
m3_ipc->mbox_client.tx_done = NULL;
|
|
m3_ipc->mbox_client.tx_prepare = NULL;
|
|
m3_ipc->mbox_client.rx_callback = NULL;
|
|
m3_ipc->mbox_client.tx_block = false;
|
|
m3_ipc->mbox_client.knows_txdone = false;
|
|
|
|
m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
|
|
|
|
if (IS_ERR(m3_ipc->mbox)) {
|
|
dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
|
|
PTR_ERR(m3_ipc->mbox));
|
|
return PTR_ERR(m3_ipc->mbox);
|
|
}
|
|
|
|
if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
|
|
dev_err(&pdev->dev, "could not get rproc phandle\n");
|
|
ret = -ENODEV;
|
|
goto err_free_mbox;
|
|
}
|
|
|
|
m3_rproc = rproc_get_by_phandle(rproc_phandle);
|
|
if (!m3_rproc) {
|
|
dev_err(&pdev->dev, "could not get rproc handle\n");
|
|
ret = -EPROBE_DEFER;
|
|
goto err_free_mbox;
|
|
}
|
|
|
|
m3_ipc->rproc = m3_rproc;
|
|
m3_ipc->dev = dev;
|
|
m3_ipc->state = M3_STATE_RESET;
|
|
|
|
m3_ipc->ops = &ipc_ops;
|
|
|
|
if (!of_property_read_u32(np, "ti,vtt-gpio-pin", &temp)) {
|
|
if (temp >= 0 && temp <= 31)
|
|
wkup_m3_set_vtt_gpio(m3_ipc, temp);
|
|
else
|
|
dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp);
|
|
}
|
|
|
|
if (of_find_property(np, "ti,set-io-isolation", NULL))
|
|
wkup_m3_set_io_isolation(m3_ipc);
|
|
|
|
ret = of_property_read_string(np, "firmware-name",
|
|
&m3_ipc->sd_fw_name);
|
|
if (ret) {
|
|
dev_dbg(dev, "Voltage scaling data blob not provided from DT.\n");
|
|
};
|
|
|
|
/*
|
|
* Wait for firmware loading completion in a thread so we
|
|
* can boot the wkup_m3 as soon as it's ready without holding
|
|
* up kernel boot
|
|
*/
|
|
task = kthread_run(wkup_m3_rproc_boot_thread, m3_ipc,
|
|
"wkup_m3_rproc_loader");
|
|
|
|
if (IS_ERR(task)) {
|
|
dev_err(dev, "can't create rproc_boot thread\n");
|
|
ret = PTR_ERR(task);
|
|
goto err_put_rproc;
|
|
}
|
|
|
|
wkup_m3_ipc_dbg_init(m3_ipc);
|
|
|
|
return 0;
|
|
|
|
err_put_rproc:
|
|
rproc_put(m3_rproc);
|
|
err_free_mbox:
|
|
mbox_free_channel(m3_ipc->mbox);
|
|
return ret;
|
|
}
|
|
|
|
static int wkup_m3_ipc_remove(struct platform_device *pdev)
|
|
{
|
|
wkup_m3_ipc_dbg_destroy(m3_ipc_state);
|
|
|
|
mbox_free_channel(m3_ipc_state->mbox);
|
|
|
|
rproc_shutdown(m3_ipc_state->rproc);
|
|
rproc_put(m3_ipc_state->rproc);
|
|
|
|
m3_ipc_state = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
|
|
{
|
|
/*
|
|
* Nothing needs to be done on suspend even with rtc_only flag set
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
|
|
{
|
|
if (m3_ipc_state->is_rtc_only) {
|
|
rproc_shutdown(m3_ipc_state->rproc);
|
|
rproc_boot(m3_ipc_state->rproc);
|
|
}
|
|
|
|
m3_ipc_state->is_rtc_only = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
|
|
};
|
|
|
|
static const struct of_device_id wkup_m3_ipc_of_match[] = {
|
|
{ .compatible = "ti,am3352-wkup-m3-ipc", },
|
|
{ .compatible = "ti,am4372-wkup-m3-ipc", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
|
|
|
|
static struct platform_driver wkup_m3_ipc_driver = {
|
|
.probe = wkup_m3_ipc_probe,
|
|
.remove = wkup_m3_ipc_remove,
|
|
.driver = {
|
|
.name = "wkup_m3_ipc",
|
|
.of_match_table = wkup_m3_ipc_of_match,
|
|
.pm = &wkup_m3_ipc_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(wkup_m3_ipc_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
|
|
MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
|