908 lines
25 KiB
C
908 lines
25 KiB
C
/*
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* File: drivers/pci/pcie/aspm.c
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* Enabling PCIe link L0s/L1 state and Clock Power Management
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*
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* Copyright (C) 2007 Intel
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* Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
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* Copyright (C) Shaohua Li (shaohua.li@intel.com)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/errno.h>
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#include <linux/pm.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/delay.h>
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#include <linux/pci-aspm.h>
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#include "../pci.h"
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#ifdef MODULE_PARAM_PREFIX
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#undef MODULE_PARAM_PREFIX
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#endif
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#define MODULE_PARAM_PREFIX "pcie_aspm."
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/* Note: those are not register definitions */
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#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
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#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
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#define ASPM_STATE_L1 (4) /* L1 state */
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#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
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#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
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struct aspm_latency {
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u32 l0s; /* L0s latency (nsec) */
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u32 l1; /* L1 latency (nsec) */
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};
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struct pcie_link_state {
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struct pci_dev *pdev; /* Upstream component of the Link */
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struct pcie_link_state *root; /* pointer to the root port link */
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struct pcie_link_state *parent; /* pointer to the parent Link state */
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struct list_head sibling; /* node in link_list */
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struct list_head children; /* list of child link states */
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struct list_head link; /* node in parent's children list */
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/* ASPM state */
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u32 aspm_support:3; /* Supported ASPM state */
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u32 aspm_enabled:3; /* Enabled ASPM state */
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u32 aspm_capable:3; /* Capable ASPM state with latency */
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u32 aspm_default:3; /* Default ASPM state by BIOS */
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u32 aspm_disable:3; /* Disabled ASPM state */
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/* Clock PM state */
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u32 clkpm_capable:1; /* Clock PM capable? */
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u32 clkpm_enabled:1; /* Current Clock PM state */
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u32 clkpm_default:1; /* Default Clock PM state by BIOS */
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/* Exit latencies */
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struct aspm_latency latency_up; /* Upstream direction exit latency */
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struct aspm_latency latency_dw; /* Downstream direction exit latency */
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/*
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* Endpoint acceptable latencies. A pcie downstream port only
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* has one slot under it, so at most there are 8 functions.
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*/
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struct aspm_latency acceptable[8];
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};
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static int aspm_disabled, aspm_force;
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static DEFINE_MUTEX(aspm_lock);
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static LIST_HEAD(link_list);
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#define POLICY_DEFAULT 0 /* BIOS default setting */
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#define POLICY_PERFORMANCE 1 /* high performance */
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#define POLICY_POWERSAVE 2 /* high power saving */
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static int aspm_policy;
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static const char *policy_str[] = {
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[POLICY_DEFAULT] = "default",
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[POLICY_PERFORMANCE] = "performance",
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[POLICY_POWERSAVE] = "powersave"
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};
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#define LINK_RETRAIN_TIMEOUT HZ
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static int policy_to_aspm_state(struct pcie_link_state *link)
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{
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switch (aspm_policy) {
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case POLICY_PERFORMANCE:
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/* Disable ASPM and Clock PM */
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return 0;
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case POLICY_POWERSAVE:
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/* Enable ASPM L0s/L1 */
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return ASPM_STATE_ALL;
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case POLICY_DEFAULT:
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return link->aspm_default;
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}
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return 0;
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}
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static int policy_to_clkpm_state(struct pcie_link_state *link)
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{
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switch (aspm_policy) {
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case POLICY_PERFORMANCE:
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/* Disable ASPM and Clock PM */
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return 0;
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case POLICY_POWERSAVE:
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/* Disable Clock PM */
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return 1;
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case POLICY_DEFAULT:
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return link->clkpm_default;
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}
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return 0;
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}
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static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
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{
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int pos;
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u16 reg16;
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struct pci_dev *child;
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struct pci_bus *linkbus = link->pdev->subordinate;
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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pos = pci_pcie_cap(child);
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if (!pos)
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return;
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pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
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if (enable)
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reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
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pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
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}
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link->clkpm_enabled = !!enable;
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}
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static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
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{
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/* Don't enable Clock PM if the link is not Clock PM capable */
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if (!link->clkpm_capable && enable)
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return;
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/* Need nothing if the specified equals to current state */
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if (link->clkpm_enabled == enable)
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return;
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pcie_set_clkpm_nocheck(link, enable);
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}
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static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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int pos, capable = 1, enabled = 1;
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u32 reg32;
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u16 reg16;
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struct pci_dev *child;
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struct pci_bus *linkbus = link->pdev->subordinate;
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/* All functions should have the same cap and state, take the worst */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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pos = pci_pcie_cap(child);
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if (!pos)
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return;
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pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32);
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if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
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capable = 0;
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enabled = 0;
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break;
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}
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pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16);
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if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
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enabled = 0;
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}
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link->clkpm_enabled = enabled;
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link->clkpm_default = enabled;
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link->clkpm_capable = (blacklist) ? 0 : capable;
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}
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/*
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* pcie_aspm_configure_common_clock: check if the 2 ends of a link
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* could use common clock. If they are, configure them to use the
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* common clock. That will reduce the ASPM state exit latency.
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*/
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static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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{
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int ppos, cpos, same_clock = 1;
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u16 reg16, parent_reg, child_reg[8];
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unsigned long start_jiffies;
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struct pci_dev *child, *parent = link->pdev;
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struct pci_bus *linkbus = parent->subordinate;
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/*
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* All functions of a slot should have the same Slot Clock
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* Configuration, so just check one function
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*/
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child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
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BUG_ON(!pci_is_pcie(child));
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/* Check downstream component if bit Slot Clock Configuration is 1 */
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cpos = pci_pcie_cap(child);
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pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_SLC))
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same_clock = 0;
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/* Check upstream component if bit Slot Clock Configuration is 1 */
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ppos = pci_pcie_cap(parent);
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pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_SLC))
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same_clock = 0;
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/* Configure downstream component, all functions */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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cpos = pci_pcie_cap(child);
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pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16);
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child_reg[PCI_FUNC(child->devfn)] = reg16;
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if (same_clock)
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reg16 |= PCI_EXP_LNKCTL_CCC;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
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}
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/* Configure upstream component */
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pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16);
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parent_reg = reg16;
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if (same_clock)
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reg16 |= PCI_EXP_LNKCTL_CCC;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
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/* Retrain link */
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reg16 |= PCI_EXP_LNKCTL_RL;
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pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
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/* Wait for link training end. Break out after waiting for timeout */
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start_jiffies = jiffies;
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for (;;) {
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pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
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break;
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msleep(1);
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}
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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return;
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/* Training failed. Restore common clock configurations */
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dev_printk(KERN_ERR, &parent->dev,
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"ASPM: Could not configure common clock\n");
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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cpos = pci_pcie_cap(child);
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pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
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child_reg[PCI_FUNC(child->devfn)]);
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}
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pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
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}
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/* Convert L0s latency encoding to ns */
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static u32 calc_l0s_latency(u32 encoding)
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{
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if (encoding == 0x7)
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return (5 * 1000); /* > 4us */
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return (64 << encoding);
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}
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/* Convert L0s acceptable latency encoding to ns */
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static u32 calc_l0s_acceptable(u32 encoding)
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{
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if (encoding == 0x7)
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return -1U;
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return (64 << encoding);
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}
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/* Convert L1 latency encoding to ns */
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static u32 calc_l1_latency(u32 encoding)
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{
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if (encoding == 0x7)
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return (65 * 1000); /* > 64us */
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return (1000 << encoding);
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}
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/* Convert L1 acceptable latency encoding to ns */
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static u32 calc_l1_acceptable(u32 encoding)
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{
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if (encoding == 0x7)
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return -1U;
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return (1000 << encoding);
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}
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struct aspm_register_info {
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u32 support:2;
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u32 enabled:2;
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u32 latency_encoding_l0s;
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u32 latency_encoding_l1;
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};
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static void pcie_get_aspm_reg(struct pci_dev *pdev,
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struct aspm_register_info *info)
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{
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int pos;
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u16 reg16;
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u32 reg32;
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pos = pci_pcie_cap(pdev);
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pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
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info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
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info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
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info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
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pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
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info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
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}
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static void pcie_aspm_check_latency(struct pci_dev *endpoint)
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{
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u32 latency, l1_switch_latency = 0;
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struct aspm_latency *acceptable;
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struct pcie_link_state *link;
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/* Device not in D0 doesn't need latency check */
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if ((endpoint->current_state != PCI_D0) &&
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(endpoint->current_state != PCI_UNKNOWN))
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return;
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link = endpoint->bus->self->link_state;
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acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
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while (link) {
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/* Check upstream direction L0s latency */
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if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
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(link->latency_up.l0s > acceptable->l0s))
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link->aspm_capable &= ~ASPM_STATE_L0S_UP;
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/* Check downstream direction L0s latency */
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if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
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(link->latency_dw.l0s > acceptable->l0s))
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link->aspm_capable &= ~ASPM_STATE_L0S_DW;
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/*
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* Check L1 latency.
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* Every switch on the path to root complex need 1
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* more microsecond for L1. Spec doesn't mention L0s.
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*/
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latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
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if ((link->aspm_capable & ASPM_STATE_L1) &&
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(latency + l1_switch_latency > acceptable->l1))
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link->aspm_capable &= ~ASPM_STATE_L1;
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l1_switch_latency += 1000;
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link = link->parent;
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}
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}
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static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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struct pci_dev *child, *parent = link->pdev;
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struct pci_bus *linkbus = parent->subordinate;
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struct aspm_register_info upreg, dwreg;
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if (blacklist) {
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/* Set enabled/disable so that we will disable ASPM later */
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link->aspm_enabled = ASPM_STATE_ALL;
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link->aspm_disable = ASPM_STATE_ALL;
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return;
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}
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/* Configure common clock before checking latencies */
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pcie_aspm_configure_common_clock(link);
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/* Get upstream/downstream components' register state */
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pcie_get_aspm_reg(parent, &upreg);
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child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
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pcie_get_aspm_reg(child, &dwreg);
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/*
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* Setup L0s state
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*
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* Note that we must not enable L0s in either direction on a
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* given link unless components on both sides of the link each
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* support L0s.
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*/
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if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
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link->aspm_support |= ASPM_STATE_L0S;
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if (dwreg.enabled & PCIE_LINK_STATE_L0S)
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link->aspm_enabled |= ASPM_STATE_L0S_UP;
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if (upreg.enabled & PCIE_LINK_STATE_L0S)
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link->aspm_enabled |= ASPM_STATE_L0S_DW;
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link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
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link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
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/* Setup L1 state */
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if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
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link->aspm_support |= ASPM_STATE_L1;
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if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
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link->aspm_enabled |= ASPM_STATE_L1;
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link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
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link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
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/* Save default state */
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link->aspm_default = link->aspm_enabled;
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/* Setup initial capable state. Will be updated later */
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link->aspm_capable = link->aspm_support;
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/*
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* If the downstream component has pci bridge function, don't
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* do ASPM for now.
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*/
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
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link->aspm_disable = ASPM_STATE_ALL;
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break;
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}
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}
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/* Get and check endpoint acceptable latencies */
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list_for_each_entry(child, &linkbus->devices, bus_list) {
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int pos;
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u32 reg32, encoding;
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struct aspm_latency *acceptable =
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&link->acceptable[PCI_FUNC(child->devfn)];
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if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
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child->pcie_type != PCI_EXP_TYPE_LEG_END)
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continue;
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pos = pci_pcie_cap(child);
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pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
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/* Calculate endpoint L0s acceptable latency */
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encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
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acceptable->l0s = calc_l0s_acceptable(encoding);
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/* Calculate endpoint L1 acceptable latency */
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encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
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acceptable->l1 = calc_l1_acceptable(encoding);
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pcie_aspm_check_latency(child);
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}
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}
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static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
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{
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u16 reg16;
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int pos = pci_pcie_cap(pdev);
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pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
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reg16 &= ~0x3;
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reg16 |= val;
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pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
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}
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static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
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{
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u32 upstream = 0, dwstream = 0;
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struct pci_dev *child, *parent = link->pdev;
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struct pci_bus *linkbus = parent->subordinate;
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/* Nothing to do if the link is already in the requested state */
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state &= (link->aspm_capable & ~link->aspm_disable);
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if (link->aspm_enabled == state)
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return;
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/* Convert ASPM state to upstream/downstream ASPM register state */
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if (state & ASPM_STATE_L0S_UP)
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dwstream |= PCIE_LINK_STATE_L0S;
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if (state & ASPM_STATE_L0S_DW)
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upstream |= PCIE_LINK_STATE_L0S;
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if (state & ASPM_STATE_L1) {
|
|
upstream |= PCIE_LINK_STATE_L1;
|
|
dwstream |= PCIE_LINK_STATE_L1;
|
|
}
|
|
/*
|
|
* Spec 2.0 suggests all functions should be configured the
|
|
* same setting for ASPM. Enabling ASPM L1 should be done in
|
|
* upstream component first and then downstream, and vice
|
|
* versa for disabling ASPM L1. Spec doesn't mention L0S.
|
|
*/
|
|
if (state & ASPM_STATE_L1)
|
|
pcie_config_aspm_dev(parent, upstream);
|
|
list_for_each_entry(child, &linkbus->devices, bus_list)
|
|
pcie_config_aspm_dev(child, dwstream);
|
|
if (!(state & ASPM_STATE_L1))
|
|
pcie_config_aspm_dev(parent, upstream);
|
|
|
|
link->aspm_enabled = state;
|
|
}
|
|
|
|
static void pcie_config_aspm_path(struct pcie_link_state *link)
|
|
{
|
|
while (link) {
|
|
pcie_config_aspm_link(link, policy_to_aspm_state(link));
|
|
link = link->parent;
|
|
}
|
|
}
|
|
|
|
static void free_link_state(struct pcie_link_state *link)
|
|
{
|
|
link->pdev->link_state = NULL;
|
|
kfree(link);
|
|
}
|
|
|
|
static int pcie_aspm_sanity_check(struct pci_dev *pdev)
|
|
{
|
|
struct pci_dev *child;
|
|
int pos;
|
|
u32 reg32;
|
|
/*
|
|
* Some functions in a slot might not all be PCIe functions,
|
|
* very strange. Disable ASPM for the whole slot
|
|
*/
|
|
list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
|
|
pos = pci_pcie_cap(child);
|
|
if (!pos)
|
|
return -EINVAL;
|
|
/*
|
|
* Disable ASPM for pre-1.1 PCIe device, we follow MS to use
|
|
* RBER bit to determine if a function is 1.1 version device
|
|
*/
|
|
pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32);
|
|
if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
|
|
dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
|
|
" on pre-1.1 PCIe device. You can enable it"
|
|
" with 'pcie_aspm=force'\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
|
|
{
|
|
struct pcie_link_state *link;
|
|
|
|
link = kzalloc(sizeof(*link), GFP_KERNEL);
|
|
if (!link)
|
|
return NULL;
|
|
INIT_LIST_HEAD(&link->sibling);
|
|
INIT_LIST_HEAD(&link->children);
|
|
INIT_LIST_HEAD(&link->link);
|
|
link->pdev = pdev;
|
|
if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
struct pcie_link_state *parent;
|
|
parent = pdev->bus->parent->self->link_state;
|
|
if (!parent) {
|
|
kfree(link);
|
|
return NULL;
|
|
}
|
|
link->parent = parent;
|
|
list_add(&link->link, &parent->children);
|
|
}
|
|
/* Setup a pointer to the root port link */
|
|
if (!link->parent)
|
|
link->root = link;
|
|
else
|
|
link->root = link->parent->root;
|
|
|
|
list_add(&link->sibling, &link_list);
|
|
pdev->link_state = link;
|
|
return link;
|
|
}
|
|
|
|
/*
|
|
* pcie_aspm_init_link_state: Initiate PCI express link state.
|
|
* It is called after the pcie and its children devices are scaned.
|
|
* @pdev: the root port or switch downstream port
|
|
*/
|
|
void pcie_aspm_init_link_state(struct pci_dev *pdev)
|
|
{
|
|
struct pcie_link_state *link;
|
|
int blacklist = !!pcie_aspm_sanity_check(pdev);
|
|
|
|
if (aspm_disabled || !pci_is_pcie(pdev) || pdev->link_state)
|
|
return;
|
|
if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
|
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
|
|
return;
|
|
|
|
/* VIA has a strange chipset, root port is under a bridge */
|
|
if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
|
|
pdev->bus->self)
|
|
return;
|
|
|
|
down_read(&pci_bus_sem);
|
|
if (list_empty(&pdev->subordinate->devices))
|
|
goto out;
|
|
|
|
mutex_lock(&aspm_lock);
|
|
link = alloc_pcie_link_state(pdev);
|
|
if (!link)
|
|
goto unlock;
|
|
/*
|
|
* Setup initial ASPM state. Note that we need to configure
|
|
* upstream links also because capable state of them can be
|
|
* update through pcie_aspm_cap_init().
|
|
*/
|
|
pcie_aspm_cap_init(link, blacklist);
|
|
pcie_config_aspm_path(link);
|
|
|
|
/* Setup initial Clock PM state */
|
|
pcie_clkpm_cap_init(link, blacklist);
|
|
pcie_set_clkpm(link, policy_to_clkpm_state(link));
|
|
unlock:
|
|
mutex_unlock(&aspm_lock);
|
|
out:
|
|
up_read(&pci_bus_sem);
|
|
}
|
|
|
|
/* Recheck latencies and update aspm_capable for links under the root */
|
|
static void pcie_update_aspm_capable(struct pcie_link_state *root)
|
|
{
|
|
struct pcie_link_state *link;
|
|
BUG_ON(root->parent);
|
|
list_for_each_entry(link, &link_list, sibling) {
|
|
if (link->root != root)
|
|
continue;
|
|
link->aspm_capable = link->aspm_support;
|
|
}
|
|
list_for_each_entry(link, &link_list, sibling) {
|
|
struct pci_dev *child;
|
|
struct pci_bus *linkbus = link->pdev->subordinate;
|
|
if (link->root != root)
|
|
continue;
|
|
list_for_each_entry(child, &linkbus->devices, bus_list) {
|
|
if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) &&
|
|
(child->pcie_type != PCI_EXP_TYPE_LEG_END))
|
|
continue;
|
|
pcie_aspm_check_latency(child);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* @pdev: the endpoint device */
|
|
void pcie_aspm_exit_link_state(struct pci_dev *pdev)
|
|
{
|
|
struct pci_dev *parent = pdev->bus->self;
|
|
struct pcie_link_state *link, *root, *parent_link;
|
|
|
|
if (aspm_disabled || !pci_is_pcie(pdev) ||
|
|
!parent || !parent->link_state)
|
|
return;
|
|
if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
|
|
(parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
|
|
return;
|
|
|
|
down_read(&pci_bus_sem);
|
|
mutex_lock(&aspm_lock);
|
|
/*
|
|
* All PCIe functions are in one slot, remove one function will remove
|
|
* the whole slot, so just wait until we are the last function left.
|
|
*/
|
|
if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
|
|
goto out;
|
|
|
|
link = parent->link_state;
|
|
root = link->root;
|
|
parent_link = link->parent;
|
|
|
|
/* All functions are removed, so just disable ASPM for the link */
|
|
pcie_config_aspm_link(link, 0);
|
|
list_del(&link->sibling);
|
|
list_del(&link->link);
|
|
/* Clock PM is for endpoint device */
|
|
free_link_state(link);
|
|
|
|
/* Recheck latencies and configure upstream links */
|
|
if (parent_link) {
|
|
pcie_update_aspm_capable(root);
|
|
pcie_config_aspm_path(parent_link);
|
|
}
|
|
out:
|
|
mutex_unlock(&aspm_lock);
|
|
up_read(&pci_bus_sem);
|
|
}
|
|
|
|
/* @pdev: the root port or switch downstream port */
|
|
void pcie_aspm_pm_state_change(struct pci_dev *pdev)
|
|
{
|
|
struct pcie_link_state *link = pdev->link_state;
|
|
|
|
if (aspm_disabled || !pci_is_pcie(pdev) || !link)
|
|
return;
|
|
if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
|
|
(pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
|
|
return;
|
|
/*
|
|
* Devices changed PM state, we should recheck if latency
|
|
* meets all functions' requirement
|
|
*/
|
|
down_read(&pci_bus_sem);
|
|
mutex_lock(&aspm_lock);
|
|
pcie_update_aspm_capable(link->root);
|
|
pcie_config_aspm_path(link);
|
|
mutex_unlock(&aspm_lock);
|
|
up_read(&pci_bus_sem);
|
|
}
|
|
|
|
/*
|
|
* pci_disable_link_state - disable pci device's link state, so the link will
|
|
* never enter specific states
|
|
*/
|
|
void pci_disable_link_state(struct pci_dev *pdev, int state)
|
|
{
|
|
struct pci_dev *parent = pdev->bus->self;
|
|
struct pcie_link_state *link;
|
|
|
|
if (aspm_disabled || !pci_is_pcie(pdev))
|
|
return;
|
|
if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
|
|
parent = pdev;
|
|
if (!parent || !parent->link_state)
|
|
return;
|
|
|
|
down_read(&pci_bus_sem);
|
|
mutex_lock(&aspm_lock);
|
|
link = parent->link_state;
|
|
if (state & PCIE_LINK_STATE_L0S)
|
|
link->aspm_disable |= ASPM_STATE_L0S;
|
|
if (state & PCIE_LINK_STATE_L1)
|
|
link->aspm_disable |= ASPM_STATE_L1;
|
|
pcie_config_aspm_link(link, policy_to_aspm_state(link));
|
|
|
|
if (state & PCIE_LINK_STATE_CLKPM) {
|
|
link->clkpm_capable = 0;
|
|
pcie_set_clkpm(link, 0);
|
|
}
|
|
mutex_unlock(&aspm_lock);
|
|
up_read(&pci_bus_sem);
|
|
}
|
|
EXPORT_SYMBOL(pci_disable_link_state);
|
|
|
|
static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
|
|
{
|
|
int i;
|
|
struct pcie_link_state *link;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(policy_str); i++)
|
|
if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
|
|
break;
|
|
if (i >= ARRAY_SIZE(policy_str))
|
|
return -EINVAL;
|
|
if (i == aspm_policy)
|
|
return 0;
|
|
|
|
down_read(&pci_bus_sem);
|
|
mutex_lock(&aspm_lock);
|
|
aspm_policy = i;
|
|
list_for_each_entry(link, &link_list, sibling) {
|
|
pcie_config_aspm_link(link, policy_to_aspm_state(link));
|
|
pcie_set_clkpm(link, policy_to_clkpm_state(link));
|
|
}
|
|
mutex_unlock(&aspm_lock);
|
|
up_read(&pci_bus_sem);
|
|
return 0;
|
|
}
|
|
|
|
static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
|
|
{
|
|
int i, cnt = 0;
|
|
for (i = 0; i < ARRAY_SIZE(policy_str); i++)
|
|
if (i == aspm_policy)
|
|
cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
|
|
else
|
|
cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
|
|
return cnt;
|
|
}
|
|
|
|
module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
|
|
NULL, 0644);
|
|
|
|
#ifdef CONFIG_PCIEASPM_DEBUG
|
|
static ssize_t link_state_show(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct pci_dev *pci_device = to_pci_dev(dev);
|
|
struct pcie_link_state *link_state = pci_device->link_state;
|
|
|
|
return sprintf(buf, "%d\n", link_state->aspm_enabled);
|
|
}
|
|
|
|
static ssize_t link_state_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf,
|
|
size_t n)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct pcie_link_state *link, *root = pdev->link_state->root;
|
|
u32 val = buf[0] - '0', state = 0;
|
|
|
|
if (n < 1 || val > 3)
|
|
return -EINVAL;
|
|
|
|
/* Convert requested state to ASPM state */
|
|
if (val & PCIE_LINK_STATE_L0S)
|
|
state |= ASPM_STATE_L0S;
|
|
if (val & PCIE_LINK_STATE_L1)
|
|
state |= ASPM_STATE_L1;
|
|
|
|
down_read(&pci_bus_sem);
|
|
mutex_lock(&aspm_lock);
|
|
list_for_each_entry(link, &link_list, sibling) {
|
|
if (link->root != root)
|
|
continue;
|
|
pcie_config_aspm_link(link, state);
|
|
}
|
|
mutex_unlock(&aspm_lock);
|
|
up_read(&pci_bus_sem);
|
|
return n;
|
|
}
|
|
|
|
static ssize_t clk_ctl_show(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct pci_dev *pci_device = to_pci_dev(dev);
|
|
struct pcie_link_state *link_state = pci_device->link_state;
|
|
|
|
return sprintf(buf, "%d\n", link_state->clkpm_enabled);
|
|
}
|
|
|
|
static ssize_t clk_ctl_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf,
|
|
size_t n)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
int state;
|
|
|
|
if (n < 1)
|
|
return -EINVAL;
|
|
state = buf[0]-'0';
|
|
|
|
down_read(&pci_bus_sem);
|
|
mutex_lock(&aspm_lock);
|
|
pcie_set_clkpm_nocheck(pdev->link_state, !!state);
|
|
mutex_unlock(&aspm_lock);
|
|
up_read(&pci_bus_sem);
|
|
|
|
return n;
|
|
}
|
|
|
|
static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
|
|
static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
|
|
|
|
static char power_group[] = "power";
|
|
void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
|
|
{
|
|
struct pcie_link_state *link_state = pdev->link_state;
|
|
|
|
if (!pci_is_pcie(pdev) ||
|
|
(pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
|
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
|
return;
|
|
|
|
if (link_state->aspm_support)
|
|
sysfs_add_file_to_group(&pdev->dev.kobj,
|
|
&dev_attr_link_state.attr, power_group);
|
|
if (link_state->clkpm_capable)
|
|
sysfs_add_file_to_group(&pdev->dev.kobj,
|
|
&dev_attr_clk_ctl.attr, power_group);
|
|
}
|
|
|
|
void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
|
|
{
|
|
struct pcie_link_state *link_state = pdev->link_state;
|
|
|
|
if (!pci_is_pcie(pdev) ||
|
|
(pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
|
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
|
|
return;
|
|
|
|
if (link_state->aspm_support)
|
|
sysfs_remove_file_from_group(&pdev->dev.kobj,
|
|
&dev_attr_link_state.attr, power_group);
|
|
if (link_state->clkpm_capable)
|
|
sysfs_remove_file_from_group(&pdev->dev.kobj,
|
|
&dev_attr_clk_ctl.attr, power_group);
|
|
}
|
|
#endif
|
|
|
|
static int __init pcie_aspm_disable(char *str)
|
|
{
|
|
if (!strcmp(str, "off")) {
|
|
aspm_disabled = 1;
|
|
printk(KERN_INFO "PCIe ASPM is disabled\n");
|
|
} else if (!strcmp(str, "force")) {
|
|
aspm_force = 1;
|
|
printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
__setup("pcie_aspm=", pcie_aspm_disable);
|
|
|
|
void pcie_no_aspm(void)
|
|
{
|
|
if (!aspm_force)
|
|
aspm_disabled = 1;
|
|
}
|
|
|
|
/**
|
|
* pcie_aspm_enabled - is PCIe ASPM enabled?
|
|
*
|
|
* Returns true if ASPM has not been disabled by the command-line option
|
|
* pcie_aspm=off.
|
|
**/
|
|
int pcie_aspm_enabled(void)
|
|
{
|
|
return !aspm_disabled;
|
|
}
|
|
EXPORT_SYMBOL(pcie_aspm_enabled);
|
|
|