781 lines
23 KiB
C
781 lines
23 KiB
C
/*
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* TLB Management (flush/create/diagnostics) for ARC700
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Aug 2011
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* -Reintroduce duplicate PD fixup - some customer chips still have the issue
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*
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* vineetg: May 2011
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* -No need to flush_cache_page( ) for each call to update_mmu_cache()
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* some of the LMBench tests improved amazingly
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* = page-fault thrice as fast (75 usec to 28 usec)
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* = mmap twice as fast (9.6 msec to 4.6 msec),
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* = fork (5.3 msec to 3.7 msec)
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*
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* vineetg: April 2011 :
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* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
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* helps avoid a shift when preparing PD0 from PTE
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*
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* vineetg: April 2011 : Preparing for MMU V3
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* -MMU v2/v3 BCRs decoded differently
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* -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
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* -tlb_entry_erase( ) can be void
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* -local_flush_tlb_range( ):
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* = need not "ceil" @end
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* = walks MMU only if range spans < 32 entries, as opposed to 256
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*
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* Vineetg: Sept 10th 2008
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* -Changes related to MMU v2 (Rel 4.8)
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*
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* Vineetg: Aug 29th 2008
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* -In TLB Flush operations (Metal Fix MMU) there is a explict command to
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* flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
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* it fails. Thus need to load it with ANY valid value before invoking
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* TLBIVUTLB cmd
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*
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* Vineetg: Aug 21th 2008:
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* -Reduced the duration of IRQ lockouts in TLB Flush routines
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* -Multiple copies of TLB erase code seperated into a "single" function
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* -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
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* in interrupt-safe region.
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*
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* Vineetg: April 23rd Bug #93131
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* Problem: tlb_flush_kernel_range() doesnt do anything if the range to
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* flush is more than the size of TLB itself.
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*
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* Rahul Trivedi : Codito Technologies 2004
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*/
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#include <linux/module.h>
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#include <linux/bug.h>
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#include <asm/arcregs.h>
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#include <asm/setup.h>
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#include <asm/mmu_context.h>
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#include <asm/mmu.h>
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/* Need for ARC MMU v2
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*
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* ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
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* For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
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* map into same set, there would be contention for the 2 ways causing severe
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* Thrashing.
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*
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* Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
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* much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
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* Given this, the thrasing problem should never happen because once the 3
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* J-TLB entries are created (even though 3rd will knock out one of the prev
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* two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
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*
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* Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
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* This is a simple design for keeping them in sync. So what do we do?
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* The solution which James came up was pretty neat. It utilised the assoc
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* of uTLBs by not invalidating always but only when absolutely necessary.
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*
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* - Existing TLB commands work as before
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* - New command (TLBWriteNI) for TLB write without clearing uTLBs
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* - New command (TLBIVUTLB) to invalidate uTLBs.
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*
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* The uTLBs need only be invalidated when pages are being removed from the
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* OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
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* as a result of a miss, the removed entry is still allowed to exist in the
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* uTLBs as it is still valid and present in the OS page table. This allows the
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* full associativity of the uTLBs to hide the limited associativity of the main
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* TLB.
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*
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* During a miss handler, the new "TLBWriteNI" command is used to load
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* entries without clearing the uTLBs.
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*
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* When the OS page table is updated, TLB entries that may be associated with a
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* removed page are removed (flushed) from the TLB using TLBWrite. In this
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* circumstance, the uTLBs must also be cleared. This is done by using the
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* existing TLBWrite command. An explicit IVUTLB is also required for those
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* corner cases when TLBWrite was not executed at all because the corresp
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* J-TLB entry got evicted/replaced.
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*/
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/* A copy of the ASID from the PID reg is kept in asid_cache */
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DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
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/*
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* Utility Routine to erase a J-TLB entry
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* Caller needs to setup Index Reg (manually or via getIndex)
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*/
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static inline void __tlb_entry_erase(void)
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{
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write_aux_reg(ARC_REG_TLBPD1, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
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{
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unsigned int idx;
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write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
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idx = read_aux_reg(ARC_REG_TLBINDEX);
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return idx;
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}
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static void tlb_entry_erase(unsigned int vaddr_n_asid)
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{
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unsigned int idx;
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/* Locate the TLB entry for this vaddr + ASID */
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idx = tlb_entry_lkup(vaddr_n_asid);
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/* No error means entry found, zero it out */
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if (likely(!(idx & TLB_LKUP_ERR))) {
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__tlb_entry_erase();
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} else {
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/* Duplicate entry error */
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WARN(idx == TLB_DUP_ERR, "Probe returned Dup PD for %x\n",
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vaddr_n_asid);
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}
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}
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/****************************************************************************
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* ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
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*
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* New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
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*
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* utlb_invalidate ( )
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* -For v2 MMU calls Flush uTLB Cmd
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* -For v1 MMU does nothing (except for Metal Fix v1 MMU)
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* This is because in v1 TLBWrite itself invalidate uTLBs
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***************************************************************************/
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static void utlb_invalidate(void)
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{
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#if (CONFIG_ARC_MMU_VER >= 2)
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#if (CONFIG_ARC_MMU_VER == 2)
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/* MMU v2 introduced the uTLB Flush command.
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* There was however an obscure hardware bug, where uTLB flush would
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* fail when a prior probe for J-TLB (both totally unrelated) would
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* return lkup err - because the entry didnt exist in MMU.
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* The Workround was to set Index reg with some valid value, prior to
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* flush. This was fixed in MMU v3 hence not needed any more
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*/
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unsigned int idx;
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/* make sure INDEX Reg is valid */
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idx = read_aux_reg(ARC_REG_TLBINDEX);
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/* If not write some dummy val */
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if (unlikely(idx & TLB_LKUP_ERR))
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write_aux_reg(ARC_REG_TLBINDEX, 0xa);
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#endif
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
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#endif
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}
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static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
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{
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unsigned int idx;
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/*
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* First verify if entry for this vaddr+ASID already exists
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* This also sets up PD0 (vaddr, ASID..) for final commit
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*/
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idx = tlb_entry_lkup(pd0);
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/*
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* If Not already present get a free slot from MMU.
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* Otherwise, Probe would have located the entry and set INDEX Reg
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* with existing location. This will cause Write CMD to over-write
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* existing entry with new PD0 and PD1
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*/
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if (likely(idx & TLB_LKUP_ERR))
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
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/* setup the other half of TLB entry (pfn, rwx..) */
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write_aux_reg(ARC_REG_TLBPD1, pd1);
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/*
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* Commit the Entry to MMU
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* It doesnt sound safe to use the TLBWriteNI cmd here
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* which doesn't flush uTLBs. I'd rather be safe than sorry.
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*/
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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/*
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* Un-conditionally (without lookup) erase the entire MMU contents
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*/
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noinline void local_flush_tlb_all(void)
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{
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unsigned long flags;
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unsigned int entry;
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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local_irq_save(flags);
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/* Load PD0 and PD1 with template for a Blank Entry */
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write_aux_reg(ARC_REG_TLBPD1, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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for (entry = 0; entry < mmu->num_tlb; entry++) {
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/* write this entry to the TLB */
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write_aux_reg(ARC_REG_TLBINDEX, entry);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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utlb_invalidate();
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local_irq_restore(flags);
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}
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/*
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* Flush the entrie MM for userland. The fastest way is to move to Next ASID
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*/
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noinline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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/*
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* Small optimisation courtesy IA64
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* flush_mm called during fork,exit,munmap etc, multiple times as well.
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* Only for fork( ) do we need to move parent to a new MMU ctxt,
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* all other cases are NOPs, hence this check.
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*/
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if (atomic_read(&mm->mm_users) == 0)
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return;
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/*
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* - Move to a new ASID, but only if the mm is still wired in
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* (Android Binder ended up calling this for vma->mm != tsk->mm,
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* causing h/w - s/w ASID to get out of sync)
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* - Also get_new_mmu_context() new implementation allocates a new
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* ASID only if it is not allocated already - so unallocate first
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*/
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destroy_context(mm);
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if (current->mm == mm)
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get_new_mmu_context(mm);
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}
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/*
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* Flush a Range of TLB entries for userland.
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* @start is inclusive, while @end is exclusive
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* Difference between this and Kernel Range Flush is
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* -Here the fastest way (if range is too large) is to move to next ASID
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* without doing any explicit Shootdown
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* -In case of kernel Flush, entry has to be shot down explictly
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*/
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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const unsigned int cpu = smp_processor_id();
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unsigned long flags;
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/* If range @start to @end is more than 32 TLB entries deep,
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* its better to move to a new ASID rather than searching for
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* individual entries and then shooting them down
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*
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* The calc above is rough, doesn't account for unaligned parts,
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* since this is heuristics based anyways
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*/
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if (unlikely((end - start) >= PAGE_SIZE * 32)) {
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local_flush_tlb_mm(vma->vm_mm);
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return;
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}
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/*
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* @start moved to page start: this alone suffices for checking
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* loop end condition below, w/o need for aligning @end to end
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* e.g. 2000 to 4001 will anyhow loop twice
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*/
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start &= PAGE_MASK;
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local_irq_save(flags);
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if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
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while (start < end) {
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tlb_entry_erase(start | hw_pid(vma->vm_mm, cpu));
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start += PAGE_SIZE;
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}
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}
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utlb_invalidate();
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local_irq_restore(flags);
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}
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/* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
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* @start, @end interpreted as kvaddr
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* Interestingly, shared TLB entries can also be flushed using just
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* @start,@end alone (interpreted as user vaddr), although technically SASID
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* is also needed. However our smart TLbProbe lookup takes care of that.
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*/
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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/* exactly same as above, except for TLB entry not taking ASID */
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if (unlikely((end - start) >= PAGE_SIZE * 32)) {
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local_flush_tlb_all();
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return;
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}
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start &= PAGE_MASK;
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local_irq_save(flags);
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while (start < end) {
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tlb_entry_erase(start);
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start += PAGE_SIZE;
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}
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utlb_invalidate();
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local_irq_restore(flags);
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}
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/*
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* Delete TLB entry in MMU for a given page (??? address)
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* NOTE One TLB entry contains translation for single PAGE
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*/
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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const unsigned int cpu = smp_processor_id();
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unsigned long flags;
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/* Note that it is critical that interrupts are DISABLED between
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* checking the ASID and using it flush the TLB entry
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*/
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local_irq_save(flags);
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if (asid_mm(vma->vm_mm, cpu) != MM_CTXT_NO_ASID) {
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tlb_entry_erase((page & PAGE_MASK) | hw_pid(vma->vm_mm, cpu));
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utlb_invalidate();
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}
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local_irq_restore(flags);
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}
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#ifdef CONFIG_SMP
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struct tlb_args {
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struct vm_area_struct *ta_vma;
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unsigned long ta_start;
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unsigned long ta_end;
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};
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static inline void ipi_flush_tlb_page(void *arg)
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{
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struct tlb_args *ta = arg;
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local_flush_tlb_page(ta->ta_vma, ta->ta_start);
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}
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static inline void ipi_flush_tlb_range(void *arg)
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{
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struct tlb_args *ta = arg;
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local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
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}
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static inline void ipi_flush_tlb_kernel_range(void *arg)
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{
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struct tlb_args *ta = (struct tlb_args *)arg;
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local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
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}
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void flush_tlb_all(void)
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{
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on_each_cpu((smp_call_func_t)local_flush_tlb_all, NULL, 1);
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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on_each_cpu_mask(mm_cpumask(mm), (smp_call_func_t)local_flush_tlb_mm,
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mm, 1);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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{
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struct tlb_args ta = {
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.ta_vma = vma,
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.ta_start = uaddr
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};
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on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_page, &ta, 1);
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct tlb_args ta = {
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.ta_vma = vma,
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.ta_start = start,
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.ta_end = end
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};
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on_each_cpu_mask(mm_cpumask(vma->vm_mm), ipi_flush_tlb_range, &ta, 1);
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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struct tlb_args ta = {
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.ta_start = start,
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.ta_end = end
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};
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on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
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}
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#endif
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/*
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* Routine to create a TLB entry
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*/
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void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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{
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unsigned long flags;
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unsigned int asid_or_sasid, rwx;
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unsigned long pd0, pd1;
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/*
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* create_tlb() assumes that current->mm == vma->mm, since
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* -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
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* -completes the lazy write to SASID reg (again valid for curr tsk)
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*
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* Removing the assumption involves
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* -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
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* -Fix the TLB paranoid debug code to not trigger false negatives.
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* -More importantly it makes this handler inconsistent with fast-path
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* TLB Refill handler which always deals with "current"
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*
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* Lets see the use cases when current->mm != vma->mm and we land here
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* 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
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* Here VM wants to pre-install a TLB entry for user stack while
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* current->mm still points to pre-execve mm (hence the condition).
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* However the stack vaddr is soon relocated (randomization) and
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* move_page_tables() tries to undo that TLB entry.
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* Thus not creating TLB entry is not any worse.
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*
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* 2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
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* breakpoint in debugged task. Not creating a TLB now is not
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* performance critical.
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*
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* Both the cases above are not good enough for code churn.
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*/
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if (current->active_mm != vma->vm_mm)
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return;
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local_irq_save(flags);
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tlb_paranoid_check(asid_mm(vma->vm_mm, smp_processor_id()), address);
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address &= PAGE_MASK;
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/* update this PTE credentials */
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pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
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/* Create HW TLB(PD0,PD1) from PTE */
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/* ASID for this task */
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asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
|
|
|
|
pd0 = address | asid_or_sasid | (pte_val(*ptep) & PTE_BITS_IN_PD0);
|
|
|
|
/*
|
|
* ARC MMU provides fully orthogonal access bits for K/U mode,
|
|
* however Linux only saves 1 set to save PTE real-estate
|
|
* Here we convert 3 PTE bits into 6 MMU bits:
|
|
* -Kernel only entries have Kr Kw Kx 0 0 0
|
|
* -User entries have mirrored K and U bits
|
|
*/
|
|
rwx = pte_val(*ptep) & PTE_BITS_RWX;
|
|
|
|
if (pte_val(*ptep) & _PAGE_GLOBAL)
|
|
rwx <<= 3; /* r w x => Kr Kw Kx 0 0 0 */
|
|
else
|
|
rwx |= (rwx << 3); /* r w x => Kr Kw Kx Ur Uw Ux */
|
|
|
|
pd1 = rwx | (pte_val(*ptep) & PTE_BITS_NON_RWX_IN_PD1);
|
|
|
|
tlb_entry_insert(pd0, pd1);
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/*
|
|
* Called at the end of pagefault, for a userspace mapped page
|
|
* -pre-install the corresponding TLB entry into MMU
|
|
* -Finalize the delayed D-cache flush of kernel mapping of page due to
|
|
* flush_dcache_page(), copy_user_page()
|
|
*
|
|
* Note that flush (when done) involves both WBACK - so physical page is
|
|
* in sync as well as INV - so any non-congruent aliases don't remain
|
|
*/
|
|
void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
|
|
pte_t *ptep)
|
|
{
|
|
unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
|
|
unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
|
|
struct page *page = pfn_to_page(pte_pfn(*ptep));
|
|
|
|
create_tlb(vma, vaddr, ptep);
|
|
|
|
if (page == ZERO_PAGE(0)) {
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Exec page : Independent of aliasing/page-color considerations,
|
|
* since icache doesn't snoop dcache on ARC, any dirty
|
|
* K-mapping of a code page needs to be wback+inv so that
|
|
* icache fetch by userspace sees code correctly.
|
|
* !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
|
|
* so userspace sees the right data.
|
|
* (Avoids the flush for Non-exec + congruent mapping case)
|
|
*/
|
|
if ((vma->vm_flags & VM_EXEC) ||
|
|
addr_not_cache_congruent(paddr, vaddr)) {
|
|
|
|
int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
|
|
if (dirty) {
|
|
/* wback + inv dcache lines */
|
|
__flush_dcache_page(paddr, paddr);
|
|
|
|
/* invalidate any existing icache lines */
|
|
if (vma->vm_flags & VM_EXEC)
|
|
__inv_icache_page(paddr, vaddr);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Read the Cache Build Confuration Registers, Decode them and save into
|
|
* the cpuinfo structure for later use.
|
|
* No Validation is done here, simply read/convert the BCRs
|
|
*/
|
|
void read_decode_mmu_bcr(void)
|
|
{
|
|
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
|
unsigned int tmp;
|
|
struct bcr_mmu_1_2 {
|
|
#ifdef CONFIG_CPU_BIG_ENDIAN
|
|
unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
|
|
#else
|
|
unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
|
|
#endif
|
|
} *mmu2;
|
|
|
|
struct bcr_mmu_3 {
|
|
#ifdef CONFIG_CPU_BIG_ENDIAN
|
|
unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
|
|
u_itlb:4, u_dtlb:4;
|
|
#else
|
|
unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
|
|
ways:4, ver:8;
|
|
#endif
|
|
} *mmu3;
|
|
|
|
tmp = read_aux_reg(ARC_REG_MMU_BCR);
|
|
mmu->ver = (tmp >> 24);
|
|
|
|
if (mmu->ver <= 2) {
|
|
mmu2 = (struct bcr_mmu_1_2 *)&tmp;
|
|
mmu->pg_sz = PAGE_SIZE;
|
|
mmu->sets = 1 << mmu2->sets;
|
|
mmu->ways = 1 << mmu2->ways;
|
|
mmu->u_dtlb = mmu2->u_dtlb;
|
|
mmu->u_itlb = mmu2->u_itlb;
|
|
} else {
|
|
mmu3 = (struct bcr_mmu_3 *)&tmp;
|
|
mmu->pg_sz = 512 << mmu3->pg_sz;
|
|
mmu->sets = 1 << mmu3->sets;
|
|
mmu->ways = 1 << mmu3->ways;
|
|
mmu->u_dtlb = mmu3->u_dtlb;
|
|
mmu->u_itlb = mmu3->u_itlb;
|
|
}
|
|
|
|
mmu->num_tlb = mmu->sets * mmu->ways;
|
|
}
|
|
|
|
char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
|
|
{
|
|
int n = 0;
|
|
struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
|
|
|
|
n += scnprintf(buf + n, len - n,
|
|
"MMU [v%x]\t: %dk PAGE, JTLB %d (%dx%d), uDTLB %d, uITLB %d %s\n",
|
|
p_mmu->ver, TO_KB(p_mmu->pg_sz),
|
|
p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
|
|
p_mmu->u_dtlb, p_mmu->u_itlb,
|
|
IS_ENABLED(CONFIG_ARC_MMU_SASID) ? ",SASID" : "");
|
|
|
|
return buf;
|
|
}
|
|
|
|
void arc_mmu_init(void)
|
|
{
|
|
char str[256];
|
|
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
|
|
|
printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
|
|
|
|
/* For efficiency sake, kernel is compile time built for a MMU ver
|
|
* This must match the hardware it is running on.
|
|
* Linux built for MMU V2, if run on MMU V1 will break down because V1
|
|
* hardware doesn't understand cmds such as WriteNI, or IVUTLB
|
|
* On the other hand, Linux built for V1 if run on MMU V2 will do
|
|
* un-needed workarounds to prevent memcpy thrashing.
|
|
* Similarly MMU V3 has new features which won't work on older MMU
|
|
*/
|
|
if (mmu->ver != CONFIG_ARC_MMU_VER) {
|
|
panic("MMU ver %d doesn't match kernel built for %d...\n",
|
|
mmu->ver, CONFIG_ARC_MMU_VER);
|
|
}
|
|
|
|
if (mmu->pg_sz != PAGE_SIZE)
|
|
panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
|
|
|
|
/* Enable the MMU */
|
|
write_aux_reg(ARC_REG_PID, MMU_ENABLE);
|
|
|
|
/* In smp we use this reg for interrupt 1 scratch */
|
|
#ifndef CONFIG_SMP
|
|
/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
|
|
write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
|
|
* The mapping is Column-first.
|
|
* --------------------- -----------
|
|
* |way0|way1|way2|way3| |way0|way1|
|
|
* --------------------- -----------
|
|
* [set0] | 0 | 1 | 2 | 3 | | 0 | 1 |
|
|
* [set1] | 4 | 5 | 6 | 7 | | 2 | 3 |
|
|
* ~ ~ ~ ~
|
|
* [set127] | 508| 509| 510| 511| | 254| 255|
|
|
* --------------------- -----------
|
|
* For normal operations we don't(must not) care how above works since
|
|
* MMU cmd getIndex(vaddr) abstracts that out.
|
|
* However for walking WAYS of a SET, we need to know this
|
|
*/
|
|
#define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way))
|
|
|
|
/* Handling of Duplicate PD (TLB entry) in MMU.
|
|
* -Could be due to buggy customer tapeouts or obscure kernel bugs
|
|
* -MMU complaints not at the time of duplicate PD installation, but at the
|
|
* time of lookup matching multiple ways.
|
|
* -Ideally these should never happen - but if they do - workaround by deleting
|
|
* the duplicate one.
|
|
* -Knob to be verbose abt it.(TODO: hook them up to debugfs)
|
|
*/
|
|
volatile int dup_pd_verbose = 1;/* Be slient abt it or complain (default) */
|
|
|
|
void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
|
|
struct pt_regs *regs)
|
|
{
|
|
int set, way, n;
|
|
unsigned long flags, is_valid;
|
|
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
|
unsigned int pd0[mmu->ways], pd1[mmu->ways];
|
|
|
|
local_irq_save(flags);
|
|
|
|
/* re-enable the MMU */
|
|
write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID));
|
|
|
|
/* loop thru all sets of TLB */
|
|
for (set = 0; set < mmu->sets; set++) {
|
|
|
|
/* read out all the ways of current set */
|
|
for (way = 0, is_valid = 0; way < mmu->ways; way++) {
|
|
write_aux_reg(ARC_REG_TLBINDEX,
|
|
SET_WAY_TO_IDX(mmu, set, way));
|
|
write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
|
|
pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
|
|
pd1[way] = read_aux_reg(ARC_REG_TLBPD1);
|
|
is_valid |= pd0[way] & _PAGE_PRESENT;
|
|
}
|
|
|
|
/* If all the WAYS in SET are empty, skip to next SET */
|
|
if (!is_valid)
|
|
continue;
|
|
|
|
/* Scan the set for duplicate ways: needs a nested loop */
|
|
for (way = 0; way < mmu->ways - 1; way++) {
|
|
if (!pd0[way])
|
|
continue;
|
|
|
|
for (n = way + 1; n < mmu->ways; n++) {
|
|
if ((pd0[way] & PAGE_MASK) ==
|
|
(pd0[n] & PAGE_MASK)) {
|
|
|
|
if (dup_pd_verbose) {
|
|
pr_info("Duplicate PD's @"
|
|
"[%d:%d]/[%d:%d]\n",
|
|
set, way, set, n);
|
|
pr_info("TLBPD0[%u]: %08x\n",
|
|
way, pd0[way]);
|
|
}
|
|
|
|
/*
|
|
* clear entry @way and not @n. This is
|
|
* critical to our optimised loop
|
|
*/
|
|
pd0[way] = pd1[way] = 0;
|
|
write_aux_reg(ARC_REG_TLBINDEX,
|
|
SET_WAY_TO_IDX(mmu, set, way));
|
|
__tlb_entry_erase();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/***********************************************************************
|
|
* Diagnostic Routines
|
|
* -Called from Low Level TLB Hanlders if things don;t look good
|
|
**********************************************************************/
|
|
|
|
#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
|
|
|
|
/*
|
|
* Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
|
|
* don't match
|
|
*/
|
|
void print_asid_mismatch(int mm_asid, int mmu_asid, int is_fast_path)
|
|
{
|
|
pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
|
|
is_fast_path ? "Fast" : "Slow", mm_asid, mmu_asid);
|
|
|
|
__asm__ __volatile__("flag 1");
|
|
}
|
|
|
|
void tlb_paranoid_check(unsigned int mm_asid, unsigned long addr)
|
|
{
|
|
unsigned int mmu_asid;
|
|
|
|
mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
|
|
|
|
/*
|
|
* At the time of a TLB miss/installation
|
|
* - HW version needs to match SW version
|
|
* - SW needs to have a valid ASID
|
|
*/
|
|
if (addr < 0x70000000 &&
|
|
((mm_asid == MM_CTXT_NO_ASID) ||
|
|
(mmu_asid != (mm_asid & MM_CTXT_ASID_MASK))))
|
|
print_asid_mismatch(mm_asid, mmu_asid, 0);
|
|
}
|
|
#endif
|