1600 lines
44 KiB
C
1600 lines
44 KiB
C
/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/sched/clock.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/mm.h>
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#include <linux/uaccess.h>
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#include <linux/delay.h>
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#include <asm/synch.h>
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#include <asm/switch_to.h>
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#include <misc/cxl-base.h>
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#include "cxl.h"
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#include "trace.h"
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static int afu_control(struct cxl_afu *afu, u64 command, u64 clear,
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u64 result, u64 mask, bool enabled)
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{
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u64 AFU_Cntl;
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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int rc = 0;
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spin_lock(&afu->afu_cntl_lock);
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pr_devel("AFU command starting: %llx\n", command);
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trace_cxl_afu_ctrl(afu, command);
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AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command);
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AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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while ((AFU_Cntl & mask) != result) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
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rc = -EBUSY;
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goto out;
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}
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if (!cxl_ops->link_ok(afu->adapter, afu)) {
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afu->enabled = enabled;
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rc = -EIO;
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goto out;
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}
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pr_devel_ratelimited("AFU control... (0x%016llx)\n",
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AFU_Cntl | command);
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cpu_relax();
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AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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}
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if (AFU_Cntl & CXL_AFU_Cntl_An_RA) {
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/*
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* Workaround for a bug in the XSL used in the Mellanox CX4
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* that fails to clear the RA bit after an AFU reset,
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* preventing subsequent AFU resets from working.
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*/
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cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA);
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}
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pr_devel("AFU command complete: %llx\n", command);
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afu->enabled = enabled;
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out:
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trace_cxl_afu_ctrl_done(afu, command, rc);
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spin_unlock(&afu->afu_cntl_lock);
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return rc;
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}
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static int afu_enable(struct cxl_afu *afu)
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{
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pr_devel("AFU enable request\n");
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return afu_control(afu, CXL_AFU_Cntl_An_E, 0,
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CXL_AFU_Cntl_An_ES_Enabled,
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CXL_AFU_Cntl_An_ES_MASK, true);
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}
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int cxl_afu_disable(struct cxl_afu *afu)
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{
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pr_devel("AFU disable request\n");
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return afu_control(afu, 0, CXL_AFU_Cntl_An_E,
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CXL_AFU_Cntl_An_ES_Disabled,
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CXL_AFU_Cntl_An_ES_MASK, false);
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}
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/* This will disable as well as reset */
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static int native_afu_reset(struct cxl_afu *afu)
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{
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int rc;
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u64 serr;
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pr_devel("AFU reset request\n");
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rc = afu_control(afu, CXL_AFU_Cntl_An_RA, 0,
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CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
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CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
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false);
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/*
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* Re-enable any masked interrupts when the AFU is not
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* activated to avoid side effects after attaching a process
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* in dedicated mode.
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*/
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if (afu->current_mode == 0) {
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serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
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serr &= ~CXL_PSL_SERR_An_IRQ_MASKS;
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cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
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}
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return rc;
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}
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static int native_afu_check_and_enable(struct cxl_afu *afu)
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{
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if (!cxl_ops->link_ok(afu->adapter, afu)) {
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WARN(1, "Refusing to enable afu while link down!\n");
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return -EIO;
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}
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if (afu->enabled)
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return 0;
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return afu_enable(afu);
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}
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int cxl_psl_purge(struct cxl_afu *afu)
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{
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u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
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u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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u64 dsisr, dar;
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u64 start, end;
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u64 trans_fault = 0x0ULL;
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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int rc = 0;
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trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
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pr_devel("PSL purge request\n");
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if (cxl_is_power8())
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trans_fault = CXL_PSL_DSISR_TRANS;
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if (cxl_is_power9())
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trans_fault = CXL_PSL9_DSISR_An_TF;
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if (!cxl_ops->link_ok(afu->adapter, afu)) {
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dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
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rc = -EIO;
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goto out;
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}
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if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
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WARN(1, "psl_purge request while AFU not disabled!\n");
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cxl_afu_disable(afu);
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}
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cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
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PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
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start = local_clock();
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PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
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while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK)
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== CXL_PSL_SCNTL_An_Ps_Pending) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
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rc = -EBUSY;
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goto out;
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}
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if (!cxl_ops->link_ok(afu->adapter, afu)) {
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rc = -EIO;
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goto out;
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}
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dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
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pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n",
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PSL_CNTL, dsisr);
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if (dsisr & trans_fault) {
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dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
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dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n",
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dsisr, dar);
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
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} else if (dsisr) {
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dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n",
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dsisr);
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
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} else {
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cpu_relax();
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}
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PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
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}
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end = local_clock();
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pr_devel("PSL purged in %lld ns\n", end - start);
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cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
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PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
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out:
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trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
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return rc;
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}
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static int spa_max_procs(int spa_size)
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{
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/*
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* From the CAIA:
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* end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
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* Most of that junk is really just an overly-complicated way of saying
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* the last 256 bytes are __aligned(128), so it's really:
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* end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
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* and
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* end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
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* so
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* sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
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* Ignore the alignment (which is safe in this case as long as we are
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* careful with our rounding) and solve for n:
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*/
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return ((spa_size / 8) - 96) / 17;
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}
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static int cxl_alloc_spa(struct cxl_afu *afu, int mode)
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{
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unsigned spa_size;
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/* Work out how many pages to allocate */
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afu->native->spa_order = -1;
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do {
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afu->native->spa_order++;
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spa_size = (1 << afu->native->spa_order) * PAGE_SIZE;
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if (spa_size > 0x100000) {
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dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n",
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afu->native->spa_max_procs, afu->native->spa_size);
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if (mode != CXL_MODE_DEDICATED)
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afu->num_procs = afu->native->spa_max_procs;
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break;
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}
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afu->native->spa_size = spa_size;
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afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size);
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} while (afu->native->spa_max_procs < afu->num_procs);
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if (!(afu->native->spa = (struct cxl_process_element *)
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__get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) {
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pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
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return -ENOMEM;
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}
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pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
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1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs);
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return 0;
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}
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static void attach_spa(struct cxl_afu *afu)
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{
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u64 spap;
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afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa +
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((afu->native->spa_max_procs + 3) * 128));
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spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr;
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spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
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spap |= CXL_PSL_SPAP_V;
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pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n",
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afu->native->spa, afu->native->spa_max_procs,
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afu->native->sw_command_status, spap);
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cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
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}
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static inline void detach_spa(struct cxl_afu *afu)
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{
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cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
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}
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void cxl_release_spa(struct cxl_afu *afu)
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{
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if (afu->native->spa) {
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free_pages((unsigned long) afu->native->spa,
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afu->native->spa_order);
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afu->native->spa = NULL;
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}
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}
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/*
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* Invalidation of all ERAT entries is no longer required by CAIA2. Use
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* only for debug.
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*/
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int cxl_invalidate_all_psl9(struct cxl *adapter)
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{
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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u64 ierat;
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pr_devel("CXL adapter - invalidation of all ERAT entries\n");
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/* Invalidates all ERAT entries for Radix or HPT */
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ierat = CXL_XSL9_IERAT_IALL;
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if (radix_enabled())
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ierat |= CXL_XSL9_IERAT_INVR;
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cxl_p1_write(adapter, CXL_XSL9_IERAT, ierat);
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while (cxl_p1_read(adapter, CXL_XSL9_IERAT) & CXL_XSL9_IERAT_IINPROG) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&adapter->dev,
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"WARNING: CXL adapter invalidation of all ERAT entries timed out!\n");
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return -EBUSY;
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}
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if (!cxl_ops->link_ok(adapter, NULL))
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return -EIO;
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cpu_relax();
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}
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return 0;
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}
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int cxl_invalidate_all_psl8(struct cxl *adapter)
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{
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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pr_devel("CXL adapter wide TLBIA & SLBIA\n");
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cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
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cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
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while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
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return -EBUSY;
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}
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if (!cxl_ops->link_ok(adapter, NULL))
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return -EIO;
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cpu_relax();
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}
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cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
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while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
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return -EBUSY;
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}
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if (!cxl_ops->link_ok(adapter, NULL))
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return -EIO;
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cpu_relax();
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}
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return 0;
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}
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int cxl_data_cache_flush(struct cxl *adapter)
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{
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u64 reg;
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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/*
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* Do a datacache flush only if datacache is available.
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* In case of PSL9D datacache absent hence flush operation.
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* would timeout.
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*/
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if (adapter->native->no_data_cache) {
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pr_devel("No PSL data cache. Ignoring cache flush req.\n");
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return 0;
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}
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pr_devel("Flushing data cache\n");
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reg = cxl_p1_read(adapter, CXL_PSL_Control);
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reg |= CXL_PSL_Control_Fr;
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cxl_p1_write(adapter, CXL_PSL_Control, reg);
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reg = cxl_p1_read(adapter, CXL_PSL_Control);
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while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n");
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return -EBUSY;
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}
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if (!cxl_ops->link_ok(adapter, NULL)) {
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dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n");
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return -EIO;
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}
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cpu_relax();
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reg = cxl_p1_read(adapter, CXL_PSL_Control);
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}
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reg &= ~CXL_PSL_Control_Fr;
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cxl_p1_write(adapter, CXL_PSL_Control, reg);
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return 0;
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}
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static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
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{
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int rc;
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/* 1. Disable SSTP by writing 0 to SSTP1[V] */
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cxl_p2n_write(afu, CXL_SSTP1_An, 0);
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/* 2. Invalidate all SLB entries */
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if ((rc = cxl_afu_slbia(afu)))
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return rc;
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/* 3. Set SSTP0_An */
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cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
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/* 4. Set SSTP1_An */
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cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
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return 0;
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}
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/* Using per slice version may improve performance here. (ie. SLBIA_An) */
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static void slb_invalid(struct cxl_context *ctx)
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{
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struct cxl *adapter = ctx->afu->adapter;
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u64 slbia;
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WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
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cxl_p1_write(adapter, CXL_PSL_LBISEL,
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((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
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be32_to_cpu(ctx->elem->lpid));
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cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
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while (1) {
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if (!cxl_ops->link_ok(adapter, NULL))
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break;
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slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
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if (!(slbia & CXL_TLB_SLB_P))
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break;
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cpu_relax();
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}
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}
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static int do_process_element_cmd(struct cxl_context *ctx,
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u64 cmd, u64 pe_state)
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{
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u64 state;
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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int rc = 0;
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|
|
trace_cxl_llcmd(ctx, cmd);
|
|
|
|
WARN_ON(!ctx->afu->enabled);
|
|
|
|
ctx->elem->software_state = cpu_to_be32(pe_state);
|
|
smp_wmb();
|
|
*(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
|
|
smp_mb();
|
|
cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
|
|
while (1) {
|
|
if (time_after_eq(jiffies, timeout)) {
|
|
dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
|
|
rc = -EBUSY;
|
|
goto out;
|
|
}
|
|
if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
|
|
dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
|
|
rc = -EIO;
|
|
goto out;
|
|
}
|
|
state = be64_to_cpup(ctx->afu->native->sw_command_status);
|
|
if (state == ~0ULL) {
|
|
pr_err("cxl: Error adding process element to AFU\n");
|
|
rc = -1;
|
|
goto out;
|
|
}
|
|
if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) ==
|
|
(cmd | (cmd >> 16) | ctx->pe))
|
|
break;
|
|
/*
|
|
* The command won't finish in the PSL if there are
|
|
* outstanding DSIs. Hence we need to yield here in
|
|
* case there are outstanding DSIs that we need to
|
|
* service. Tuning possiblity: we could wait for a
|
|
* while before sched
|
|
*/
|
|
schedule();
|
|
|
|
}
|
|
out:
|
|
trace_cxl_llcmd_done(ctx, cmd, rc);
|
|
return rc;
|
|
}
|
|
|
|
static int add_process_element(struct cxl_context *ctx)
|
|
{
|
|
int rc = 0;
|
|
|
|
mutex_lock(&ctx->afu->native->spa_mutex);
|
|
pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
|
|
if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
|
|
ctx->pe_inserted = true;
|
|
pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
|
|
mutex_unlock(&ctx->afu->native->spa_mutex);
|
|
return rc;
|
|
}
|
|
|
|
static int terminate_process_element(struct cxl_context *ctx)
|
|
{
|
|
int rc = 0;
|
|
|
|
/* fast path terminate if it's already invalid */
|
|
if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
|
|
return rc;
|
|
|
|
mutex_lock(&ctx->afu->native->spa_mutex);
|
|
pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
|
|
/* We could be asked to terminate when the hw is down. That
|
|
* should always succeed: it's not running if the hw has gone
|
|
* away and is being reset.
|
|
*/
|
|
if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
|
|
rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
|
|
CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
|
|
ctx->elem->software_state = 0; /* Remove Valid bit */
|
|
pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
|
|
mutex_unlock(&ctx->afu->native->spa_mutex);
|
|
return rc;
|
|
}
|
|
|
|
static int remove_process_element(struct cxl_context *ctx)
|
|
{
|
|
int rc = 0;
|
|
|
|
mutex_lock(&ctx->afu->native->spa_mutex);
|
|
pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
|
|
|
|
/* We could be asked to remove when the hw is down. Again, if
|
|
* the hw is down, the PE is gone, so we succeed.
|
|
*/
|
|
if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
|
|
rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
|
|
|
|
if (!rc)
|
|
ctx->pe_inserted = false;
|
|
if (cxl_is_power8())
|
|
slb_invalid(ctx);
|
|
pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
|
|
mutex_unlock(&ctx->afu->native->spa_mutex);
|
|
|
|
return rc;
|
|
}
|
|
|
|
void cxl_assign_psn_space(struct cxl_context *ctx)
|
|
{
|
|
if (!ctx->afu->pp_size || ctx->master) {
|
|
ctx->psn_phys = ctx->afu->psn_phys;
|
|
ctx->psn_size = ctx->afu->adapter->ps_size;
|
|
} else {
|
|
ctx->psn_phys = ctx->afu->psn_phys +
|
|
(ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
|
|
ctx->psn_size = ctx->afu->pp_size;
|
|
}
|
|
}
|
|
|
|
static int activate_afu_directed(struct cxl_afu *afu)
|
|
{
|
|
int rc;
|
|
|
|
dev_info(&afu->dev, "Activating AFU directed mode\n");
|
|
|
|
afu->num_procs = afu->max_procs_virtualised;
|
|
if (afu->native->spa == NULL) {
|
|
if (cxl_alloc_spa(afu, CXL_MODE_DIRECTED))
|
|
return -ENOMEM;
|
|
}
|
|
attach_spa(afu);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
|
|
if (cxl_is_power8())
|
|
cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
|
|
cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
|
|
|
|
afu->current_mode = CXL_MODE_DIRECTED;
|
|
|
|
if ((rc = cxl_chardev_m_afu_add(afu)))
|
|
return rc;
|
|
|
|
if ((rc = cxl_sysfs_afu_m_add(afu)))
|
|
goto err;
|
|
|
|
if ((rc = cxl_chardev_s_afu_add(afu)))
|
|
goto err1;
|
|
|
|
return 0;
|
|
err1:
|
|
cxl_sysfs_afu_m_remove(afu);
|
|
err:
|
|
cxl_chardev_afu_remove(afu);
|
|
return rc;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
|
#define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
|
|
#else
|
|
#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
|
|
#endif
|
|
|
|
u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9)
|
|
{
|
|
u64 sr = 0;
|
|
|
|
set_endian(sr);
|
|
if (master)
|
|
sr |= CXL_PSL_SR_An_MP;
|
|
if (mfspr(SPRN_LPCR) & LPCR_TC)
|
|
sr |= CXL_PSL_SR_An_TC;
|
|
if (kernel) {
|
|
if (!real_mode)
|
|
sr |= CXL_PSL_SR_An_R;
|
|
sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
|
|
} else {
|
|
sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
|
|
if (radix_enabled())
|
|
sr |= CXL_PSL_SR_An_HV;
|
|
else
|
|
sr &= ~(CXL_PSL_SR_An_HV);
|
|
if (!test_tsk_thread_flag(current, TIF_32BIT))
|
|
sr |= CXL_PSL_SR_An_SF;
|
|
}
|
|
if (p9) {
|
|
if (radix_enabled())
|
|
sr |= CXL_PSL_SR_An_XLAT_ror;
|
|
else
|
|
sr |= CXL_PSL_SR_An_XLAT_hpt;
|
|
}
|
|
return sr;
|
|
}
|
|
|
|
static u64 calculate_sr(struct cxl_context *ctx)
|
|
{
|
|
return cxl_calculate_sr(ctx->master, ctx->kernel, ctx->real_mode,
|
|
cxl_is_power9());
|
|
}
|
|
|
|
static void update_ivtes_directed(struct cxl_context *ctx)
|
|
{
|
|
bool need_update = (ctx->status == STARTED);
|
|
int r;
|
|
|
|
if (need_update) {
|
|
WARN_ON(terminate_process_element(ctx));
|
|
WARN_ON(remove_process_element(ctx));
|
|
}
|
|
|
|
for (r = 0; r < CXL_IRQ_RANGES; r++) {
|
|
ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
|
|
ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
|
|
}
|
|
|
|
/*
|
|
* Theoretically we could use the update llcmd, instead of a
|
|
* terminate/remove/add (or if an atomic update was required we could
|
|
* do a suspend/update/resume), however it seems there might be issues
|
|
* with the update llcmd on some cards (including those using an XSL on
|
|
* an ASIC) so for now it's safest to go with the commands that are
|
|
* known to work. In the future if we come across a situation where the
|
|
* card may be performing transactions using the same PE while we are
|
|
* doing this update we might need to revisit this.
|
|
*/
|
|
if (need_update)
|
|
WARN_ON(add_process_element(ctx));
|
|
}
|
|
|
|
static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
|
|
{
|
|
u32 pid;
|
|
int rc;
|
|
|
|
cxl_assign_psn_space(ctx);
|
|
|
|
ctx->elem->ctxtime = 0; /* disable */
|
|
ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
|
|
ctx->elem->haurp = 0; /* disable */
|
|
|
|
if (ctx->kernel)
|
|
pid = 0;
|
|
else {
|
|
if (ctx->mm == NULL) {
|
|
pr_devel("%s: unable to get mm for pe=%d pid=%i\n",
|
|
__func__, ctx->pe, pid_nr(ctx->pid));
|
|
return -EINVAL;
|
|
}
|
|
pid = ctx->mm->context.id;
|
|
}
|
|
|
|
/* Assign a unique TIDR (thread id) for the current thread */
|
|
if (!(ctx->tidr) && (ctx->assign_tidr)) {
|
|
rc = set_thread_tidr(current);
|
|
if (rc)
|
|
return -ENODEV;
|
|
ctx->tidr = current->thread.tidr;
|
|
pr_devel("%s: current tidr: %d\n", __func__, ctx->tidr);
|
|
}
|
|
|
|
ctx->elem->common.tid = cpu_to_be32(ctx->tidr);
|
|
ctx->elem->common.pid = cpu_to_be32(pid);
|
|
|
|
ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
|
|
|
|
ctx->elem->common.csrp = 0; /* disable */
|
|
|
|
cxl_prefault(ctx, wed);
|
|
|
|
/*
|
|
* Ensure we have the multiplexed PSL interrupt set up to take faults
|
|
* for kernel contexts that may not have allocated any AFU IRQs at all:
|
|
*/
|
|
if (ctx->irqs.range[0] == 0) {
|
|
ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
|
|
ctx->irqs.range[0] = 1;
|
|
}
|
|
|
|
ctx->elem->common.amr = cpu_to_be64(amr);
|
|
ctx->elem->common.wed = cpu_to_be64(wed);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
|
|
{
|
|
int result;
|
|
|
|
/* fill the process element entry */
|
|
result = process_element_entry_psl9(ctx, wed, amr);
|
|
if (result)
|
|
return result;
|
|
|
|
update_ivtes_directed(ctx);
|
|
|
|
/* first guy needs to enable */
|
|
result = cxl_ops->afu_check_and_enable(ctx->afu);
|
|
if (result)
|
|
return result;
|
|
|
|
return add_process_element(ctx);
|
|
}
|
|
|
|
int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
|
|
{
|
|
u32 pid;
|
|
int result;
|
|
|
|
cxl_assign_psn_space(ctx);
|
|
|
|
ctx->elem->ctxtime = 0; /* disable */
|
|
ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
|
|
ctx->elem->haurp = 0; /* disable */
|
|
ctx->elem->u.sdr = cpu_to_be64(mfspr(SPRN_SDR1));
|
|
|
|
pid = current->pid;
|
|
if (ctx->kernel)
|
|
pid = 0;
|
|
ctx->elem->common.tid = 0;
|
|
ctx->elem->common.pid = cpu_to_be32(pid);
|
|
|
|
ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
|
|
|
|
ctx->elem->common.csrp = 0; /* disable */
|
|
ctx->elem->common.u.psl8.aurp0 = 0; /* disable */
|
|
ctx->elem->common.u.psl8.aurp1 = 0; /* disable */
|
|
|
|
cxl_prefault(ctx, wed);
|
|
|
|
ctx->elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
|
|
ctx->elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
|
|
|
|
/*
|
|
* Ensure we have the multiplexed PSL interrupt set up to take faults
|
|
* for kernel contexts that may not have allocated any AFU IRQs at all:
|
|
*/
|
|
if (ctx->irqs.range[0] == 0) {
|
|
ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
|
|
ctx->irqs.range[0] = 1;
|
|
}
|
|
|
|
update_ivtes_directed(ctx);
|
|
|
|
ctx->elem->common.amr = cpu_to_be64(amr);
|
|
ctx->elem->common.wed = cpu_to_be64(wed);
|
|
|
|
/* first guy needs to enable */
|
|
if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
|
|
return result;
|
|
|
|
return add_process_element(ctx);
|
|
}
|
|
|
|
static int deactivate_afu_directed(struct cxl_afu *afu)
|
|
{
|
|
dev_info(&afu->dev, "Deactivating AFU directed mode\n");
|
|
|
|
afu->current_mode = 0;
|
|
afu->num_procs = 0;
|
|
|
|
cxl_sysfs_afu_m_remove(afu);
|
|
cxl_chardev_afu_remove(afu);
|
|
|
|
/*
|
|
* The CAIA section 2.2.1 indicates that the procedure for starting and
|
|
* stopping an AFU in AFU directed mode is AFU specific, which is not
|
|
* ideal since this code is generic and with one exception has no
|
|
* knowledge of the AFU. This is in contrast to the procedure for
|
|
* disabling a dedicated process AFU, which is documented to just
|
|
* require a reset. The architecture does indicate that both an AFU
|
|
* reset and an AFU disable should result in the AFU being disabled and
|
|
* we do both followed by a PSL purge for safety.
|
|
*
|
|
* Notably we used to have some issues with the disable sequence on PSL
|
|
* cards, which is why we ended up using this heavy weight procedure in
|
|
* the first place, however a bug was discovered that had rendered the
|
|
* disable operation ineffective, so it is conceivable that was the
|
|
* sole explanation for those difficulties. Careful regression testing
|
|
* is recommended if anyone attempts to remove or reorder these
|
|
* operations.
|
|
*
|
|
* The XSL on the Mellanox CX4 behaves a little differently from the
|
|
* PSL based cards and will time out an AFU reset if the AFU is still
|
|
* enabled. That card is special in that we do have a means to identify
|
|
* it from this code, so in that case we skip the reset and just use a
|
|
* disable/purge to avoid the timeout and corresponding noise in the
|
|
* kernel log.
|
|
*/
|
|
if (afu->adapter->native->sl_ops->needs_reset_before_disable)
|
|
cxl_ops->afu_reset(afu);
|
|
cxl_afu_disable(afu);
|
|
cxl_psl_purge(afu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu)
|
|
{
|
|
dev_info(&afu->dev, "Activating dedicated process mode\n");
|
|
|
|
/*
|
|
* If XSL is set to dedicated mode (Set in PSL_SCNTL reg), the
|
|
* XSL and AFU are programmed to work with a single context.
|
|
* The context information should be configured in the SPA area
|
|
* index 0 (so PSL_SPAP must be configured before enabling the
|
|
* AFU).
|
|
*/
|
|
afu->num_procs = 1;
|
|
if (afu->native->spa == NULL) {
|
|
if (cxl_alloc_spa(afu, CXL_MODE_DEDICATED))
|
|
return -ENOMEM;
|
|
}
|
|
attach_spa(afu);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
|
|
cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
|
|
|
|
afu->current_mode = CXL_MODE_DEDICATED;
|
|
|
|
return cxl_chardev_d_afu_add(afu);
|
|
}
|
|
|
|
int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu)
|
|
{
|
|
dev_info(&afu->dev, "Activating dedicated process mode\n");
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
|
|
cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */
|
|
cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
|
|
cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
|
|
cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */
|
|
cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
|
|
|
|
cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */
|
|
cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */
|
|
cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */
|
|
|
|
afu->current_mode = CXL_MODE_DEDICATED;
|
|
afu->num_procs = 1;
|
|
|
|
return cxl_chardev_d_afu_add(afu);
|
|
}
|
|
|
|
void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx)
|
|
{
|
|
int r;
|
|
|
|
for (r = 0; r < CXL_IRQ_RANGES; r++) {
|
|
ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
|
|
ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
|
|
}
|
|
}
|
|
|
|
void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
|
|
{
|
|
struct cxl_afu *afu = ctx->afu;
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
|
|
(((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
|
|
(((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
|
|
(((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
|
|
((u64)ctx->irqs.offset[3] & 0xffff));
|
|
cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
|
|
(((u64)ctx->irqs.range[0] & 0xffff) << 48) |
|
|
(((u64)ctx->irqs.range[1] & 0xffff) << 32) |
|
|
(((u64)ctx->irqs.range[2] & 0xffff) << 16) |
|
|
((u64)ctx->irqs.range[3] & 0xffff));
|
|
}
|
|
|
|
int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
|
|
{
|
|
struct cxl_afu *afu = ctx->afu;
|
|
int result;
|
|
|
|
/* fill the process element entry */
|
|
result = process_element_entry_psl9(ctx, wed, amr);
|
|
if (result)
|
|
return result;
|
|
|
|
if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
|
|
afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
|
|
|
|
ctx->elem->software_state = cpu_to_be32(CXL_PE_SOFTWARE_STATE_V);
|
|
/*
|
|
* Ideally we should do a wmb() here to make sure the changes to the
|
|
* PE are visible to the card before we call afu_enable.
|
|
* On ppc64 though all mmios are preceded by a 'sync' instruction hence
|
|
* we dont dont need one here.
|
|
*/
|
|
|
|
result = cxl_ops->afu_reset(afu);
|
|
if (result)
|
|
return result;
|
|
|
|
return afu_enable(afu);
|
|
}
|
|
|
|
int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
|
|
{
|
|
struct cxl_afu *afu = ctx->afu;
|
|
u64 pid;
|
|
int rc;
|
|
|
|
pid = (u64)current->pid << 32;
|
|
if (ctx->kernel)
|
|
pid = 0;
|
|
cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
|
|
|
|
if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
|
|
return rc;
|
|
|
|
cxl_prefault(ctx, wed);
|
|
|
|
if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
|
|
afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
|
|
|
|
cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
|
|
|
|
/* master only context for dedicated */
|
|
cxl_assign_psn_space(ctx);
|
|
|
|
if ((rc = cxl_ops->afu_reset(afu)))
|
|
return rc;
|
|
|
|
cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
|
|
|
|
return afu_enable(afu);
|
|
}
|
|
|
|
static int deactivate_dedicated_process(struct cxl_afu *afu)
|
|
{
|
|
dev_info(&afu->dev, "Deactivating dedicated process mode\n");
|
|
|
|
afu->current_mode = 0;
|
|
afu->num_procs = 0;
|
|
|
|
cxl_chardev_afu_remove(afu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode)
|
|
{
|
|
if (mode == CXL_MODE_DIRECTED)
|
|
return deactivate_afu_directed(afu);
|
|
if (mode == CXL_MODE_DEDICATED)
|
|
return deactivate_dedicated_process(afu);
|
|
return 0;
|
|
}
|
|
|
|
static int native_afu_activate_mode(struct cxl_afu *afu, int mode)
|
|
{
|
|
if (!mode)
|
|
return 0;
|
|
if (!(mode & afu->modes_supported))
|
|
return -EINVAL;
|
|
|
|
if (!cxl_ops->link_ok(afu->adapter, afu)) {
|
|
WARN(1, "Device link is down, refusing to activate!\n");
|
|
return -EIO;
|
|
}
|
|
|
|
if (mode == CXL_MODE_DIRECTED)
|
|
return activate_afu_directed(afu);
|
|
if ((mode == CXL_MODE_DEDICATED) &&
|
|
(afu->adapter->native->sl_ops->activate_dedicated_process))
|
|
return afu->adapter->native->sl_ops->activate_dedicated_process(afu);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int native_attach_process(struct cxl_context *ctx, bool kernel,
|
|
u64 wed, u64 amr)
|
|
{
|
|
if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
|
|
WARN(1, "Device link is down, refusing to attach process!\n");
|
|
return -EIO;
|
|
}
|
|
|
|
ctx->kernel = kernel;
|
|
if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) &&
|
|
(ctx->afu->adapter->native->sl_ops->attach_afu_directed))
|
|
return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr);
|
|
|
|
if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
|
|
(ctx->afu->adapter->native->sl_ops->attach_dedicated_process))
|
|
return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static inline int detach_process_native_dedicated(struct cxl_context *ctx)
|
|
{
|
|
/*
|
|
* The CAIA section 2.1.1 indicates that we need to do an AFU reset to
|
|
* stop the AFU in dedicated mode (we therefore do not make that
|
|
* optional like we do in the afu directed path). It does not indicate
|
|
* that we need to do an explicit disable (which should occur
|
|
* implicitly as part of the reset) or purge, but we do these as well
|
|
* to be on the safe side.
|
|
*
|
|
* Notably we used to have some issues with the disable sequence
|
|
* (before the sequence was spelled out in the architecture) which is
|
|
* why we were so heavy weight in the first place, however a bug was
|
|
* discovered that had rendered the disable operation ineffective, so
|
|
* it is conceivable that was the sole explanation for those
|
|
* difficulties. Point is, we should be careful and do some regression
|
|
* testing if we ever attempt to remove any part of this procedure.
|
|
*/
|
|
cxl_ops->afu_reset(ctx->afu);
|
|
cxl_afu_disable(ctx->afu);
|
|
cxl_psl_purge(ctx->afu);
|
|
return 0;
|
|
}
|
|
|
|
static void native_update_ivtes(struct cxl_context *ctx)
|
|
{
|
|
if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
|
|
return update_ivtes_directed(ctx);
|
|
if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
|
|
(ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes))
|
|
return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
|
|
WARN(1, "native_update_ivtes: Bad mode\n");
|
|
}
|
|
|
|
static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
|
|
{
|
|
if (!ctx->pe_inserted)
|
|
return 0;
|
|
if (terminate_process_element(ctx))
|
|
return -1;
|
|
if (remove_process_element(ctx))
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int native_detach_process(struct cxl_context *ctx)
|
|
{
|
|
trace_cxl_detach(ctx);
|
|
|
|
if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
|
|
return detach_process_native_dedicated(ctx);
|
|
|
|
return detach_process_native_afu_directed(ctx);
|
|
}
|
|
|
|
static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
|
|
{
|
|
/* If the adapter has gone away, we can't get any meaningful
|
|
* information.
|
|
*/
|
|
if (!cxl_ops->link_ok(afu->adapter, afu))
|
|
return -EIO;
|
|
|
|
info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
|
|
info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
|
|
if (cxl_is_power8())
|
|
info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
|
|
info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
|
|
info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
|
|
info->proc_handle = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)
|
|
{
|
|
u64 fir1, serr;
|
|
|
|
fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
|
|
|
|
dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
|
|
if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
|
|
serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
|
|
cxl_afu_decode_psl_serr(ctx->afu, serr);
|
|
}
|
|
}
|
|
|
|
void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx)
|
|
{
|
|
u64 fir1, fir2, fir_slice, serr, afu_debug;
|
|
|
|
fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
|
|
fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
|
|
fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
|
|
afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
|
|
|
|
dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
|
|
dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
|
|
if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
|
|
serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
|
|
cxl_afu_decode_psl_serr(ctx->afu, serr);
|
|
}
|
|
dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
|
|
dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
|
|
}
|
|
|
|
static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
|
|
u64 dsisr, u64 errstat)
|
|
{
|
|
|
|
dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
|
|
|
|
if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers)
|
|
ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx);
|
|
|
|
if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) {
|
|
dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
|
|
ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter);
|
|
}
|
|
|
|
return cxl_ops->ack_irq(ctx, 0, errstat);
|
|
}
|
|
|
|
static bool cxl_is_translation_fault(struct cxl_afu *afu, u64 dsisr)
|
|
{
|
|
if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_TRANS))
|
|
return true;
|
|
|
|
if ((cxl_is_power9()) && (dsisr & CXL_PSL9_DSISR_An_TF))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
|
|
{
|
|
if (cxl_is_translation_fault(afu, irq_info->dsisr))
|
|
cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
|
|
else
|
|
cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t native_irq_multiplexed(int irq, void *data)
|
|
{
|
|
struct cxl_afu *afu = data;
|
|
struct cxl_context *ctx;
|
|
struct cxl_irq_info irq_info;
|
|
u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An);
|
|
int ph, ret = IRQ_HANDLED, res;
|
|
|
|
/* check if eeh kicked in while the interrupt was in flight */
|
|
if (unlikely(phreg == ~0ULL)) {
|
|
dev_warn(&afu->dev,
|
|
"Ignoring slice interrupt(%d) due to fenced card",
|
|
irq);
|
|
return IRQ_HANDLED;
|
|
}
|
|
/* Mask the pe-handle from register value */
|
|
ph = phreg & 0xffff;
|
|
if ((res = native_get_irq_info(afu, &irq_info))) {
|
|
WARN(1, "Unable to get CXL IRQ Info: %i\n", res);
|
|
if (afu->adapter->native->sl_ops->fail_irq)
|
|
return afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
|
|
return ret;
|
|
}
|
|
|
|
rcu_read_lock();
|
|
ctx = idr_find(&afu->contexts_idr, ph);
|
|
if (ctx) {
|
|
if (afu->adapter->native->sl_ops->handle_interrupt)
|
|
ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info);
|
|
rcu_read_unlock();
|
|
return ret;
|
|
}
|
|
rcu_read_unlock();
|
|
|
|
WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
|
|
" %016llx\n(Possible AFU HW issue - was a term/remove acked"
|
|
" with outstanding transactions?)\n", ph, irq_info.dsisr,
|
|
irq_info.dar);
|
|
if (afu->adapter->native->sl_ops->fail_irq)
|
|
ret = afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
|
|
return ret;
|
|
}
|
|
|
|
static void native_irq_wait(struct cxl_context *ctx)
|
|
{
|
|
u64 dsisr;
|
|
int timeout = 1000;
|
|
int ph;
|
|
|
|
/*
|
|
* Wait until no further interrupts are presented by the PSL
|
|
* for this context.
|
|
*/
|
|
while (timeout--) {
|
|
ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
|
|
if (ph != ctx->pe)
|
|
return;
|
|
dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
|
|
if (cxl_is_power8() &&
|
|
((dsisr & CXL_PSL_DSISR_PENDING) == 0))
|
|
return;
|
|
if (cxl_is_power9() &&
|
|
((dsisr & CXL_PSL9_DSISR_PENDING) == 0))
|
|
return;
|
|
/*
|
|
* We are waiting for the workqueue to process our
|
|
* irq, so need to let that run here.
|
|
*/
|
|
msleep(1);
|
|
}
|
|
|
|
dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
|
|
" DSISR %016llx!\n", ph, dsisr);
|
|
return;
|
|
}
|
|
|
|
static irqreturn_t native_slice_irq_err(int irq, void *data)
|
|
{
|
|
struct cxl_afu *afu = data;
|
|
u64 errstat, serr, afu_error, dsisr;
|
|
u64 fir_slice, afu_debug, irq_mask;
|
|
|
|
/*
|
|
* slice err interrupt is only used with full PSL (no XSL)
|
|
*/
|
|
serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
|
|
errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
|
|
afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
|
|
dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
|
|
cxl_afu_decode_psl_serr(afu, serr);
|
|
|
|
if (cxl_is_power8()) {
|
|
fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
|
|
afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
|
|
dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
|
|
dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
|
|
}
|
|
dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
|
|
dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
|
|
dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
|
|
|
|
/* mask off the IRQ so it won't retrigger until the AFU is reset */
|
|
irq_mask = (serr & CXL_PSL_SERR_An_IRQS) >> 32;
|
|
serr |= irq_mask;
|
|
cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
|
|
dev_info(&afu->dev, "Further such interrupts will be masked until the AFU is reset\n");
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter)
|
|
{
|
|
u64 fir1;
|
|
|
|
fir1 = cxl_p1_read(adapter, CXL_PSL9_FIR1);
|
|
dev_crit(&adapter->dev, "PSL_FIR: 0x%016llx\n", fir1);
|
|
}
|
|
|
|
void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter)
|
|
{
|
|
u64 fir1, fir2;
|
|
|
|
fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
|
|
fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
|
|
dev_crit(&adapter->dev,
|
|
"PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n",
|
|
fir1, fir2);
|
|
}
|
|
|
|
static irqreturn_t native_irq_err(int irq, void *data)
|
|
{
|
|
struct cxl *adapter = data;
|
|
u64 err_ivte;
|
|
|
|
WARN(1, "CXL ERROR interrupt %i\n", irq);
|
|
|
|
err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
|
|
dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
|
|
|
|
if (adapter->native->sl_ops->debugfs_stop_trace) {
|
|
dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
|
|
adapter->native->sl_ops->debugfs_stop_trace(adapter);
|
|
}
|
|
|
|
if (adapter->native->sl_ops->err_irq_dump_registers)
|
|
adapter->native->sl_ops->err_irq_dump_registers(adapter);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int cxl_native_register_psl_err_irq(struct cxl *adapter)
|
|
{
|
|
int rc;
|
|
|
|
adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
|
|
dev_name(&adapter->dev));
|
|
if (!adapter->irq_name)
|
|
return -ENOMEM;
|
|
|
|
if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter,
|
|
&adapter->native->err_hwirq,
|
|
&adapter->native->err_virq,
|
|
adapter->irq_name))) {
|
|
kfree(adapter->irq_name);
|
|
adapter->irq_name = NULL;
|
|
return rc;
|
|
}
|
|
|
|
cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void cxl_native_release_psl_err_irq(struct cxl *adapter)
|
|
{
|
|
if (adapter->native->err_virq == 0 ||
|
|
adapter->native->err_virq !=
|
|
irq_find_mapping(NULL, adapter->native->err_hwirq))
|
|
return;
|
|
|
|
cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
|
|
cxl_unmap_irq(adapter->native->err_virq, adapter);
|
|
cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq);
|
|
kfree(adapter->irq_name);
|
|
adapter->native->err_virq = 0;
|
|
}
|
|
|
|
int cxl_native_register_serr_irq(struct cxl_afu *afu)
|
|
{
|
|
u64 serr;
|
|
int rc;
|
|
|
|
afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
|
|
dev_name(&afu->dev));
|
|
if (!afu->err_irq_name)
|
|
return -ENOMEM;
|
|
|
|
if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu,
|
|
&afu->serr_hwirq,
|
|
&afu->serr_virq, afu->err_irq_name))) {
|
|
kfree(afu->err_irq_name);
|
|
afu->err_irq_name = NULL;
|
|
return rc;
|
|
}
|
|
|
|
serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
|
|
if (cxl_is_power8())
|
|
serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
|
|
if (cxl_is_power9()) {
|
|
/*
|
|
* By default, all errors are masked. So don't set all masks.
|
|
* Slice errors will be transfered.
|
|
*/
|
|
serr = (serr & ~0xff0000007fffffffULL) | (afu->serr_hwirq & 0xffff);
|
|
}
|
|
cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void cxl_native_release_serr_irq(struct cxl_afu *afu)
|
|
{
|
|
if (afu->serr_virq == 0 ||
|
|
afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
|
|
return;
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
|
|
cxl_unmap_irq(afu->serr_virq, afu);
|
|
cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
|
|
kfree(afu->err_irq_name);
|
|
afu->serr_virq = 0;
|
|
}
|
|
|
|
int cxl_native_register_psl_irq(struct cxl_afu *afu)
|
|
{
|
|
int rc;
|
|
|
|
afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
|
|
dev_name(&afu->dev));
|
|
if (!afu->psl_irq_name)
|
|
return -ENOMEM;
|
|
|
|
if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed,
|
|
afu, &afu->native->psl_hwirq, &afu->native->psl_virq,
|
|
afu->psl_irq_name))) {
|
|
kfree(afu->psl_irq_name);
|
|
afu->psl_irq_name = NULL;
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
void cxl_native_release_psl_irq(struct cxl_afu *afu)
|
|
{
|
|
if (afu->native->psl_virq == 0 ||
|
|
afu->native->psl_virq !=
|
|
irq_find_mapping(NULL, afu->native->psl_hwirq))
|
|
return;
|
|
|
|
cxl_unmap_irq(afu->native->psl_virq, afu);
|
|
cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq);
|
|
kfree(afu->psl_irq_name);
|
|
afu->native->psl_virq = 0;
|
|
}
|
|
|
|
static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
|
|
{
|
|
u64 dsisr;
|
|
|
|
pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
|
|
|
|
/* Clear PSL_DSISR[PE] */
|
|
dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
|
|
cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
|
|
|
|
/* Write 1s to clear error status bits */
|
|
cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
|
|
}
|
|
|
|
static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
|
|
{
|
|
trace_cxl_psl_irq_ack(ctx, tfc);
|
|
if (tfc)
|
|
cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
|
|
if (psl_reset_mask)
|
|
recover_psl_err(ctx->afu, psl_reset_mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cxl_check_error(struct cxl_afu *afu)
|
|
{
|
|
return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
|
|
}
|
|
|
|
static bool native_support_attributes(const char *attr_name,
|
|
enum cxl_attrs type)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
|
|
{
|
|
if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
|
|
return -EIO;
|
|
if (unlikely(off >= afu->crs_len))
|
|
return -ERANGE;
|
|
*out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
|
|
(cr * afu->crs_len) + off);
|
|
return 0;
|
|
}
|
|
|
|
static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out)
|
|
{
|
|
if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
|
|
return -EIO;
|
|
if (unlikely(off >= afu->crs_len))
|
|
return -ERANGE;
|
|
*out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset +
|
|
(cr * afu->crs_len) + off);
|
|
return 0;
|
|
}
|
|
|
|
static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out)
|
|
{
|
|
u64 aligned_off = off & ~0x3L;
|
|
u32 val;
|
|
int rc;
|
|
|
|
rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
|
|
if (!rc)
|
|
*out = (val >> ((off & 0x3) * 8)) & 0xffff;
|
|
return rc;
|
|
}
|
|
|
|
static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
|
|
{
|
|
u64 aligned_off = off & ~0x3L;
|
|
u32 val;
|
|
int rc;
|
|
|
|
rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
|
|
if (!rc)
|
|
*out = (val >> ((off & 0x3) * 8)) & 0xff;
|
|
return rc;
|
|
}
|
|
|
|
static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
|
|
{
|
|
if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
|
|
return -EIO;
|
|
if (unlikely(off >= afu->crs_len))
|
|
return -ERANGE;
|
|
out_le32(afu->native->afu_desc_mmio + afu->crs_offset +
|
|
(cr * afu->crs_len) + off, in);
|
|
return 0;
|
|
}
|
|
|
|
static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
|
|
{
|
|
u64 aligned_off = off & ~0x3L;
|
|
u32 val32, mask, shift;
|
|
int rc;
|
|
|
|
rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
|
|
if (rc)
|
|
return rc;
|
|
shift = (off & 0x3) * 8;
|
|
WARN_ON(shift == 24);
|
|
mask = 0xffff << shift;
|
|
val32 = (val32 & ~mask) | (in << shift);
|
|
|
|
rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
|
|
return rc;
|
|
}
|
|
|
|
static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
|
|
{
|
|
u64 aligned_off = off & ~0x3L;
|
|
u32 val32, mask, shift;
|
|
int rc;
|
|
|
|
rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
|
|
if (rc)
|
|
return rc;
|
|
shift = (off & 0x3) * 8;
|
|
mask = 0xff << shift;
|
|
val32 = (val32 & ~mask) | (in << shift);
|
|
|
|
rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
|
|
return rc;
|
|
}
|
|
|
|
const struct cxl_backend_ops cxl_native_ops = {
|
|
.module = THIS_MODULE,
|
|
.adapter_reset = cxl_pci_reset,
|
|
.alloc_one_irq = cxl_pci_alloc_one_irq,
|
|
.release_one_irq = cxl_pci_release_one_irq,
|
|
.alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
|
|
.release_irq_ranges = cxl_pci_release_irq_ranges,
|
|
.setup_irq = cxl_pci_setup_irq,
|
|
.handle_psl_slice_error = native_handle_psl_slice_error,
|
|
.psl_interrupt = NULL,
|
|
.ack_irq = native_ack_irq,
|
|
.irq_wait = native_irq_wait,
|
|
.attach_process = native_attach_process,
|
|
.detach_process = native_detach_process,
|
|
.update_ivtes = native_update_ivtes,
|
|
.support_attributes = native_support_attributes,
|
|
.link_ok = cxl_adapter_link_ok,
|
|
.release_afu = cxl_pci_release_afu,
|
|
.afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
|
|
.afu_check_and_enable = native_afu_check_and_enable,
|
|
.afu_activate_mode = native_afu_activate_mode,
|
|
.afu_deactivate_mode = native_afu_deactivate_mode,
|
|
.afu_reset = native_afu_reset,
|
|
.afu_cr_read8 = native_afu_cr_read8,
|
|
.afu_cr_read16 = native_afu_cr_read16,
|
|
.afu_cr_read32 = native_afu_cr_read32,
|
|
.afu_cr_read64 = native_afu_cr_read64,
|
|
.afu_cr_write8 = native_afu_cr_write8,
|
|
.afu_cr_write16 = native_afu_cr_write16,
|
|
.afu_cr_write32 = native_afu_cr_write32,
|
|
.read_adapter_vpd = cxl_pci_read_adapter_vpd,
|
|
};
|