55 lines
1.3 KiB
YAML
55 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
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maintainers:
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- Wen He <wen.he_1@nxp.com>
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description: |
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NXP LS1028A has a clock domain PXLCLK0 used for the Display output
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interface in the display core, as implemented in TSMC CLN28HPM PLL.
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which generate and offers pixel clocks to Display.
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properties:
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compatible:
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const: fsl,ls1028a-plldig
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reg:
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maxItems: 1
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'#clock-cells':
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const: 0
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fsl,vco-hz:
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description: Optional for VCO frequency of the PLL in Hertz.
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The VCO frequency of this PLL cannot be changed during runtime
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only at startup. Therefore, the output frequencies are very
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limited and might not even closely match the requested frequency.
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To work around this restriction the user may specify its own
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desired VCO frequency for the PLL.
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minimum: 650000000
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maximum: 1300000000
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default: 1188000000
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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examples:
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# Display PIXEL Clock node:
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- |
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dpclk: clock-display@f1f0000 {
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compatible = "fsl,ls1028a-plldig";
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reg = <0x0 0xf1f0000 0x0 0xffff>;
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#clock-cells = <0>;
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clocks = <&osc_27m>;
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};
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...
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