36 lines
853 B
C
36 lines
853 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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/* Video Clock */
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#ifndef __MESON_VCLK_H
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#define __MESON_VCLK_H
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#include <drm/drm_modes.h>
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struct meson_drm;
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enum {
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MESON_VCLK_TARGET_CVBS = 0,
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MESON_VCLK_TARGET_HDMI = 1,
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MESON_VCLK_TARGET_DMT = 2,
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};
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/* 27MHz is the CVBS Pixel Clock */
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#define MESON_VCLK_CVBS 27000
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enum drm_mode_status
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meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
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enum drm_mode_status
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meson_vclk_vic_supported_freq(unsigned int phy_freq, unsigned int vclk_freq);
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void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
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unsigned int phy_freq, unsigned int vclk_freq,
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unsigned int venc_freq, unsigned int dac_freq,
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bool hdmi_use_enci);
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#endif /* __MESON_VCLK_H */
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