179 lines
5.6 KiB
C
179 lines
5.6 KiB
C
/*
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* Copyright 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* FIXME: resolve with the i915 version
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*/
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#include "psb_drv.h"
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#define PCI_ASLE 0xe4
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#define PCI_ASLS 0xfc
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#define OPREGION_HEADER_OFFSET 0
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#define OPREGION_ACPI_OFFSET 0x100
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#define ACPI_CLID 0x01ac /* current lid state indicator */
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#define ACPI_CDCK 0x01b0 /* current docking state indicator */
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#define OPREGION_SWSCI_OFFSET 0x200
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#define OPREGION_ASLE_OFFSET 0x300
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#define OPREGION_VBT_OFFSET 0x400
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#define OPREGION_SIGNATURE "IntelGraphicsMem"
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#define MBOX_ACPI (1<<0)
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#define MBOX_SWSCI (1<<1)
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#define MBOX_ASLE (1<<2)
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struct opregion_header {
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u8 signature[16];
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u32 size;
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u32 opregion_ver;
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u8 bios_ver[32];
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u8 vbios_ver[16];
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u8 driver_ver[16];
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u32 mboxes;
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u8 reserved[164];
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} __packed;
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/* OpRegion mailbox #1: public ACPI methods */
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struct opregion_acpi {
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u32 drdy; /* driver readiness */
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u32 csts; /* notification status */
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u32 cevt; /* current event */
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u8 rsvd1[20];
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u32 didl[8]; /* supported display devices ID list */
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u32 cpdl[8]; /* currently presented display list */
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u32 cadl[8]; /* currently active display list */
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u32 nadl[8]; /* next active devices list */
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u32 aslp; /* ASL sleep time-out */
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u32 tidx; /* toggle table index */
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u32 chpd; /* current hotplug enable indicator */
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u32 clid; /* current lid state*/
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u32 cdck; /* current docking state */
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u32 sxsw; /* Sx state resume */
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u32 evts; /* ASL supported events */
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u32 cnot; /* current OS notification */
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u32 nrdy; /* driver status */
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u8 rsvd2[60];
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} __attribute__((packed));
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/* OpRegion mailbox #2: SWSCI */
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struct opregion_swsci {
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u32 scic; /* SWSCI command|status|data */
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u32 parm; /* command parameters */
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u32 dslp; /* driver sleep time-out */
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u8 rsvd[244];
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} __attribute__((packed));
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/* OpRegion mailbox #3: ASLE */
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struct opregion_asle {
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u32 ardy; /* driver readiness */
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u32 aslc; /* ASLE interrupt command */
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u32 tche; /* technology enabled indicator */
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u32 alsi; /* current ALS illuminance reading */
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u32 bclp; /* backlight brightness to set */
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u32 pfit; /* panel fitting state */
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u32 cblv; /* current brightness level */
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u16 bclm[20]; /* backlight level duty cycle mapping table */
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u32 cpfm; /* current panel fitting mode */
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u32 epfm; /* enabled panel fitting modes */
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u8 plut[74]; /* panel LUT and identifier */
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u32 pfmb; /* PWM freq and min brightness */
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u8 rsvd[102];
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} __attribute__((packed));
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/* ASLE irq request bits */
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#define ASLE_SET_ALS_ILLUM (1 << 0)
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#define ASLE_SET_BACKLIGHT (1 << 1)
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#define ASLE_SET_PFIT (1 << 2)
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#define ASLE_SET_PWM_FREQ (1 << 3)
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#define ASLE_REQ_MSK 0xf
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/* response bits of ASLE irq request */
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#define ASLE_ALS_ILLUM_FAILED (1<<10)
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#define ASLE_BACKLIGHT_FAILED (1<<12)
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#define ASLE_PFIT_FAILED (1<<14)
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#define ASLE_PWM_FREQ_FAILED (1<<16)
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/* ASLE backlight brightness to set */
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#define ASLE_BCLP_VALID (1<<31)
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#define ASLE_BCLP_MSK (~(1<<31))
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/* ASLE panel fitting request */
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#define ASLE_PFIT_VALID (1<<31)
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#define ASLE_PFIT_CENTER (1<<0)
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#define ASLE_PFIT_STRETCH_TEXT (1<<1)
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#define ASLE_PFIT_STRETCH_GFX (1<<2)
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/* PWM frequency and minimum brightness */
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#define ASLE_PFMB_BRIGHTNESS_MASK (0xff)
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#define ASLE_PFMB_BRIGHTNESS_VALID (1<<8)
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#define ASLE_PFMB_PWM_MASK (0x7ffffe00)
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#define ASLE_PFMB_PWM_VALID (1<<31)
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#define ASLE_CBLV_VALID (1<<31)
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#define ACPI_OTHER_OUTPUT (0<<8)
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#define ACPI_VGA_OUTPUT (1<<8)
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#define ACPI_TV_OUTPUT (2<<8)
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#define ACPI_DIGITAL_OUTPUT (3<<8)
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#define ACPI_LVDS_OUTPUT (4<<8)
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int gma_intel_opregion_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_opregion *opregion = &dev_priv->opregion;
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u32 opregion_phy;
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void *base;
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u32 *lid_state;
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dev_priv->lid_state = NULL;
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pci_read_config_dword(dev->pdev, 0xfc, &opregion_phy);
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if (opregion_phy == 0)
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return -ENOTSUPP;
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base = ioremap(opregion_phy, 8*1024);
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if (!base)
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return -ENOMEM;
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/* FIXME: should use _io ops - ditto on i915 */
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if (memcmp(base, OPREGION_SIGNATURE, 16)) {
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DRM_ERROR("opregion signature mismatch\n");
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iounmap(base);
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return -EINVAL;
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}
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lid_state = base + 0x01ac;
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dev_priv->lid_state = lid_state;
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dev_priv->lid_last_state = readl(lid_state);
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opregion->header = base;
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opregion->vbt = base + OPREGION_VBT_OFFSET;
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return 0;
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}
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int gma_intel_opregion_exit(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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if (dev_priv->opregion.header)
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iounmap(dev_priv->opregion.header);
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return 0;
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}
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