688 lines
23 KiB
C
688 lines
23 KiB
C
/*
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* Copyright (C) 1999 - 2010 Intel Corporation.
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* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
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*
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* This code was derived from the Intel e1000e Linux driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PCH_GBE_H_
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#define _PCH_GBE_H_
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/mii.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/vmalloc.h>
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#include <net/ip.h>
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#include <net/tcp.h>
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#include <net/udp.h>
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/**
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* pch_gbe_regs_mac_adr - Structure holding values of mac address registers
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* @high Denotes the 1st to 4th byte from the initial of MAC address
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* @low Denotes the 5th to 6th byte from the initial of MAC address
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*/
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struct pch_gbe_regs_mac_adr {
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u32 high;
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u32 low;
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};
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/**
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* pch_udc_regs - Structure holding values of MAC registers
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*/
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struct pch_gbe_regs {
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u32 INT_ST;
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u32 INT_EN;
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u32 MODE;
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u32 RESET;
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u32 TCPIP_ACC;
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u32 EX_LIST;
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u32 INT_ST_HOLD;
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u32 PHY_INT_CTRL;
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u32 MAC_RX_EN;
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u32 RX_FCTRL;
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u32 PAUSE_REQ;
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u32 RX_MODE;
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u32 TX_MODE;
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u32 RX_FIFO_ST;
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u32 TX_FIFO_ST;
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u32 TX_FID;
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u32 TX_RESULT;
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u32 PAUSE_PKT1;
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u32 PAUSE_PKT2;
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u32 PAUSE_PKT3;
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u32 PAUSE_PKT4;
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u32 PAUSE_PKT5;
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u32 reserve[2];
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struct pch_gbe_regs_mac_adr mac_adr[16];
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u32 ADDR_MASK;
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u32 MIIM;
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u32 MAC_ADDR_LOAD;
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u32 RGMII_ST;
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u32 RGMII_CTRL;
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u32 reserve3[3];
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u32 DMA_CTRL;
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u32 reserve4[3];
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u32 RX_DSC_BASE;
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u32 RX_DSC_SIZE;
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u32 RX_DSC_HW_P;
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u32 RX_DSC_HW_P_HLD;
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u32 RX_DSC_SW_P;
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u32 reserve5[3];
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u32 TX_DSC_BASE;
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u32 TX_DSC_SIZE;
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u32 TX_DSC_HW_P;
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u32 TX_DSC_HW_P_HLD;
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u32 TX_DSC_SW_P;
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u32 reserve6[3];
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u32 RX_DMA_ST;
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u32 TX_DMA_ST;
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u32 reserve7[2];
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u32 WOL_ST;
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u32 WOL_CTRL;
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u32 WOL_ADDR_MASK;
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};
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/* Interrupt Status */
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/* Interrupt Status Hold */
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/* Interrupt Enable */
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#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */
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#define PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */
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#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */
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#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */
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#define PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */
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#define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */
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#define PCH_GBE_INT_TX_CMPLT 0x00000100 /* MAC Transmission Complete */
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#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 /* DMA Transfer Complete */
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#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */
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#define PCH_GBE_INT_TX_DMA_ERR 0x00000800 /* Transmission DMA Error */
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#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 /* Pause Transmission complete */
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#define PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */
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#define PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */
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#define PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */
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#define PCH_GBE_INT_TCPIP_ERR 0x10000000 /* TCP/IP Accelerator Error */
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/* Mode */
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#define PCH_GBE_MODE_MII_ETHER 0x00000000 /* GIGA Ethernet Mode [MII] */
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#define PCH_GBE_MODE_GMII_ETHER 0x80000000 /* GIGA Ethernet Mode [GMII] */
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#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 /* Duplex Mode [half duplex] */
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#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */
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#define PCH_GBE_MODE_FR_BST 0x04000000 /* Frame bursting is done */
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/* Reset */
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#define PCH_GBE_ALL_RST 0x80000000 /* All reset */
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#define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */
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#define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */
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/* TCP/IP Accelerator Control */
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#define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */
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#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */
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#define PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */
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#define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */
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/* MAC RX Enable */
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#define PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */
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/* RX Flow Control */
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#define PCH_GBE_FL_CTRL_EN 0x80000000 /* Pause packet is enabled */
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/* Pause Packet Request */
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#define PCH_GBE_PS_PKT_RQ 0x80000000 /* Pause packet Request */
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/* RX Mode */
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#define PCH_GBE_ADD_FIL_EN 0x80000000 /* Address Filtering Enable */
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/* Multicast Filtering Enable */
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#define PCH_GBE_MLT_FIL_EN 0x40000000
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/* Receive Almost Empty Threshold */
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#define PCH_GBE_RH_ALM_EMP_4 0x00000000 /* 4 words */
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#define PCH_GBE_RH_ALM_EMP_8 0x00004000 /* 8 words */
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#define PCH_GBE_RH_ALM_EMP_16 0x00008000 /* 16 words */
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#define PCH_GBE_RH_ALM_EMP_32 0x0000C000 /* 32 words */
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/* Receive Almost Full Threshold */
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#define PCH_GBE_RH_ALM_FULL_4 0x00000000 /* 4 words */
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#define PCH_GBE_RH_ALM_FULL_8 0x00001000 /* 8 words */
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#define PCH_GBE_RH_ALM_FULL_16 0x00002000 /* 16 words */
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#define PCH_GBE_RH_ALM_FULL_32 0x00003000 /* 32 words */
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/* RX FIFO Read Triger Threshold */
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#define PCH_GBE_RH_RD_TRG_4 0x00000000 /* 4 words */
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#define PCH_GBE_RH_RD_TRG_8 0x00000200 /* 8 words */
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#define PCH_GBE_RH_RD_TRG_16 0x00000400 /* 16 words */
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#define PCH_GBE_RH_RD_TRG_32 0x00000600 /* 32 words */
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#define PCH_GBE_RH_RD_TRG_64 0x00000800 /* 64 words */
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#define PCH_GBE_RH_RD_TRG_128 0x00000A00 /* 128 words */
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#define PCH_GBE_RH_RD_TRG_256 0x00000C00 /* 256 words */
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#define PCH_GBE_RH_RD_TRG_512 0x00000E00 /* 512 words */
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/* Receive Descriptor bit definitions */
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#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
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#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
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#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
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#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000C0
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#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
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#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
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#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
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#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
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#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
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#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
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#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
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#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
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#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
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#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
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#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
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#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
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#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
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#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
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#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
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#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
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#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
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#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
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/* Transmit Descriptor bit definitions */
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#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
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#define PCH_GBE_TXD_CTRL_ITAG 0x0004
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#define PCH_GBE_TXD_CTRL_ICRC 0x0002
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#define PCH_GBE_TXD_CTRL_APAD 0x0001
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#define PCH_GBE_TXD_WORDS_SHIFT 2
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#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
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#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
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#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
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#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
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#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
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#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
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#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
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#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
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#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
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#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
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#define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK 0x000F
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/* TX Mode */
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#define PCH_GBE_TM_NO_RTRY 0x80000000 /* No Retransmission */
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#define PCH_GBE_TM_LONG_PKT 0x40000000 /* Long Packt TX Enable */
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#define PCH_GBE_TM_ST_AND_FD 0x20000000 /* Stare and Forward */
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#define PCH_GBE_TM_SHORT_PKT 0x10000000 /* Short Packet TX Enable */
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#define PCH_GBE_TM_LTCOL_RETX 0x08000000 /* Retransmission at Late Collision */
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/* Frame Start Threshold */
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#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 /* 4 words */
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#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 /* 8 words */
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#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 /* 16 words */
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#define PCH_GBE_TM_TH_TX_STRT_32 0x0000C000 /* 32 words */
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/* Transmit Almost Empty Threshold */
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#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 /* 4 words */
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#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 /* 8 words */
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#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 /* 16 words */
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#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 /* 32 words */
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#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 /* 64 words */
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#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 /* 128 words */
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#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 /* 256 words */
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#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 /* 512 words */
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/* Transmit Almost Full Threshold */
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#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 /* 4 words */
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#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 /* 8 words */
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#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 /* 16 words */
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#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 /* 32 words */
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/* RX FIFO Status */
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#define PCH_GBE_RF_ALM_FULL 0x80000000 /* RX FIFO is almost full. */
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#define PCH_GBE_RF_ALM_EMP 0x40000000 /* RX FIFO is almost empty. */
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#define PCH_GBE_RF_RD_TRG 0x20000000 /* Become more than RH_RD_TRG. */
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#define PCH_GBE_RF_STRWD 0x1FFE0000 /* The word count of RX FIFO. */
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#define PCH_GBE_RF_RCVING 0x00010000 /* Stored in RX FIFO. */
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/* MAC Address Mask */
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#define PCH_GBE_BUSY 0x80000000
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/* MIIM */
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#define PCH_GBE_MIIM_OPER_WRITE 0x04000000
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#define PCH_GBE_MIIM_OPER_READ 0x00000000
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#define PCH_GBE_MIIM_OPER_READY 0x04000000
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#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
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#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
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/* RGMII Status */
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#define PCH_GBE_LINK_UP 0x80000008
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#define PCH_GBE_RXC_SPEED_MSK 0x00000006
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#define PCH_GBE_RXC_SPEED_2_5M 0x00000000 /* 2.5MHz */
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#define PCH_GBE_RXC_SPEED_25M 0x00000002 /* 25MHz */
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#define PCH_GBE_RXC_SPEED_125M 0x00000004 /* 100MHz */
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#define PCH_GBE_DUPLEX_FULL 0x00000001
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/* RGMII Control */
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#define PCH_GBE_CRS_SEL 0x00000010
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#define PCH_GBE_RGMII_RATE_125M 0x00000000
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#define PCH_GBE_RGMII_RATE_25M 0x00000008
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#define PCH_GBE_RGMII_RATE_2_5M 0x0000000C
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#define PCH_GBE_RGMII_MODE_GMII 0x00000000
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#define PCH_GBE_RGMII_MODE_RGMII 0x00000002
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#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
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#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
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/* DMA Control */
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#define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */
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#define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */
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/* RX DMA STATUS */
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#define PCH_GBE_IDLE_CHECK 0xFFFFFFFE
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/* Wake On LAN Status */
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#define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */
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#define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */
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/* The Frame registered in Address Recognizer */
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#define PCH_GBE_WLS_IND 0x00000002
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#define PCH_GBE_WLS_MP 0x00000001 /* Magic packet Address */
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/* Wake On LAN Control */
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#define PCH_GBE_WLC_WOL_MODE 0x00010000
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#define PCH_GBE_WLC_IGN_TLONG 0x00000100
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#define PCH_GBE_WLC_IGN_TSHRT 0x00000080
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#define PCH_GBE_WLC_IGN_OCTER 0x00000040
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#define PCH_GBE_WLC_IGN_NBLER 0x00000020
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#define PCH_GBE_WLC_IGN_CRCER 0x00000010
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#define PCH_GBE_WLC_BR 0x00000008
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#define PCH_GBE_WLC_MLT 0x00000004
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#define PCH_GBE_WLC_IND 0x00000002
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#define PCH_GBE_WLC_MP 0x00000001
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/* Wake On LAN Address Mask */
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#define PCH_GBE_WLA_BUSY 0x80000000
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/* TX/RX descriptor defines */
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#define PCH_GBE_MAX_TXD 4096
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#define PCH_GBE_DEFAULT_TXD 256
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#define PCH_GBE_MIN_TXD 8
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#define PCH_GBE_MAX_RXD 4096
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#define PCH_GBE_DEFAULT_RXD 256
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#define PCH_GBE_MIN_RXD 8
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/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
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#define PCH_GBE_TX_DESC_MULTIPLE 8
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#define PCH_GBE_RX_DESC_MULTIPLE 8
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/* Read/Write operation is done through MII Management IF */
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#define PCH_GBE_HAL_MIIM_READ ((u32)0x00000000)
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#define PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000)
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/* flow control values */
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#define PCH_GBE_FC_NONE 0
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#define PCH_GBE_FC_RX_PAUSE 1
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#define PCH_GBE_FC_TX_PAUSE 2
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#define PCH_GBE_FC_FULL 3
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#define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL
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struct pch_gbe_hw;
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/**
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* struct pch_gbe_functions - HAL APi function pointer
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* @get_bus_info: for pch_gbe_hal_get_bus_info
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* @init_hw: for pch_gbe_hal_init_hw
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* @read_phy_reg: for pch_gbe_hal_read_phy_reg
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* @write_phy_reg: for pch_gbe_hal_write_phy_reg
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* @reset_phy: for pch_gbe_hal_phy_hw_reset
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* @sw_reset_phy: for pch_gbe_hal_phy_sw_reset
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* @power_up_phy: for pch_gbe_hal_power_up_phy
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* @power_down_phy: for pch_gbe_hal_power_down_phy
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* @read_mac_addr: for pch_gbe_hal_read_mac_addr
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*/
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struct pch_gbe_functions {
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void (*get_bus_info) (struct pch_gbe_hw *);
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s32 (*init_hw) (struct pch_gbe_hw *);
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s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
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s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
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void (*reset_phy) (struct pch_gbe_hw *);
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void (*sw_reset_phy) (struct pch_gbe_hw *);
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void (*power_up_phy) (struct pch_gbe_hw *hw);
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void (*power_down_phy) (struct pch_gbe_hw *hw);
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s32 (*read_mac_addr) (struct pch_gbe_hw *);
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};
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/**
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* struct pch_gbe_mac_info - MAC information
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* @addr[6]: Store the MAC address
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* @fc: Mode of flow control
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* @fc_autoneg: Auto negotiation enable for flow control setting
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* @tx_fc_enable: Enable flag of Transmit flow control
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* @max_frame_size: Max transmit frame size
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* @min_frame_size: Min transmit frame size
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* @autoneg: Auto negotiation enable
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* @link_speed: Link speed
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* @link_duplex: Link duplex
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*/
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struct pch_gbe_mac_info {
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u8 addr[6];
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u8 fc;
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u8 fc_autoneg;
|
|
u8 tx_fc_enable;
|
|
u32 max_frame_size;
|
|
u32 min_frame_size;
|
|
u8 autoneg;
|
|
u16 link_speed;
|
|
u16 link_duplex;
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_phy_info - PHY information
|
|
* @addr: PHY address
|
|
* @id: PHY's identifier
|
|
* @revision: PHY's revision
|
|
* @reset_delay_us: HW reset delay time[us]
|
|
* @autoneg_advertised: Autoneg advertised
|
|
*/
|
|
struct pch_gbe_phy_info {
|
|
u32 addr;
|
|
u32 id;
|
|
u32 revision;
|
|
u32 reset_delay_us;
|
|
u16 autoneg_advertised;
|
|
};
|
|
|
|
/*!
|
|
* @ingroup Gigabit Ether driver Layer
|
|
* @struct pch_gbe_bus_info
|
|
* @brief Bus information
|
|
*/
|
|
struct pch_gbe_bus_info {
|
|
u8 type;
|
|
u8 speed;
|
|
u8 width;
|
|
};
|
|
|
|
/*!
|
|
* @ingroup Gigabit Ether driver Layer
|
|
* @struct pch_gbe_hw
|
|
* @brief Hardware information
|
|
*/
|
|
struct pch_gbe_hw {
|
|
void *back;
|
|
|
|
struct pch_gbe_regs __iomem *reg;
|
|
spinlock_t miim_lock;
|
|
|
|
const struct pch_gbe_functions *func;
|
|
struct pch_gbe_mac_info mac;
|
|
struct pch_gbe_phy_info phy;
|
|
struct pch_gbe_bus_info bus;
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_rx_desc - Receive Descriptor
|
|
* @buffer_addr: RX Frame Buffer Address
|
|
* @tcp_ip_status: TCP/IP Accelerator Status
|
|
* @rx_words_eob: RX word count and Byte position
|
|
* @gbec_status: GMAC Status
|
|
* @dma_status: DMA Status
|
|
* @reserved1: Reserved
|
|
* @reserved2: Reserved
|
|
*/
|
|
struct pch_gbe_rx_desc {
|
|
u32 buffer_addr;
|
|
u32 tcp_ip_status;
|
|
u16 rx_words_eob;
|
|
u16 gbec_status;
|
|
u8 dma_status;
|
|
u8 reserved1;
|
|
u16 reserved2;
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_tx_desc - Transmit Descriptor
|
|
* @buffer_addr: TX Frame Buffer Address
|
|
* @length: Data buffer length
|
|
* @reserved1: Reserved
|
|
* @tx_words_eob: TX word count and Byte position
|
|
* @tx_frame_ctrl: TX Frame Control
|
|
* @dma_status: DMA Status
|
|
* @reserved2: Reserved
|
|
* @gbec_status: GMAC Status
|
|
*/
|
|
struct pch_gbe_tx_desc {
|
|
u32 buffer_addr;
|
|
u16 length;
|
|
u16 reserved1;
|
|
u16 tx_words_eob;
|
|
u16 tx_frame_ctrl;
|
|
u8 dma_status;
|
|
u8 reserved2;
|
|
u16 gbec_status;
|
|
};
|
|
|
|
|
|
/**
|
|
* struct pch_gbe_buffer - Buffer information
|
|
* @skb: pointer to a socket buffer
|
|
* @dma: DMA address
|
|
* @time_stamp: time stamp
|
|
* @length: data size
|
|
*/
|
|
struct pch_gbe_buffer {
|
|
struct sk_buff *skb;
|
|
dma_addr_t dma;
|
|
unsigned char *rx_buffer;
|
|
unsigned long time_stamp;
|
|
u16 length;
|
|
bool mapped;
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_tx_ring - tx ring information
|
|
* @desc: pointer to the descriptor ring memory
|
|
* @dma: physical address of the descriptor ring
|
|
* @size: length of descriptor ring in bytes
|
|
* @count: number of descriptors in the ring
|
|
* @next_to_use: next descriptor to associate a buffer with
|
|
* @next_to_clean: next descriptor to check for DD status bit
|
|
* @buffer_info: array of buffer information structs
|
|
*/
|
|
struct pch_gbe_tx_ring {
|
|
struct pch_gbe_tx_desc *desc;
|
|
dma_addr_t dma;
|
|
unsigned int size;
|
|
unsigned int count;
|
|
unsigned int next_to_use;
|
|
unsigned int next_to_clean;
|
|
struct pch_gbe_buffer *buffer_info;
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_rx_ring - rx ring information
|
|
* @desc: pointer to the descriptor ring memory
|
|
* @dma: physical address of the descriptor ring
|
|
* @size: length of descriptor ring in bytes
|
|
* @count: number of descriptors in the ring
|
|
* @next_to_use: next descriptor to associate a buffer with
|
|
* @next_to_clean: next descriptor to check for DD status bit
|
|
* @buffer_info: array of buffer information structs
|
|
*/
|
|
struct pch_gbe_rx_ring {
|
|
struct pch_gbe_rx_desc *desc;
|
|
dma_addr_t dma;
|
|
unsigned char *rx_buff_pool;
|
|
dma_addr_t rx_buff_pool_logic;
|
|
unsigned int rx_buff_pool_size;
|
|
unsigned int size;
|
|
unsigned int count;
|
|
unsigned int next_to_use;
|
|
unsigned int next_to_clean;
|
|
struct pch_gbe_buffer *buffer_info;
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_hw_stats - Statistics counters collected by the MAC
|
|
* @rx_packets: total packets received
|
|
* @tx_packets: total packets transmitted
|
|
* @rx_bytes: total bytes received
|
|
* @tx_bytes: total bytes transmitted
|
|
* @rx_errors: bad packets received
|
|
* @tx_errors: packet transmit problems
|
|
* @rx_dropped: no space in Linux buffers
|
|
* @tx_dropped: no space available in Linux
|
|
* @multicast: multicast packets received
|
|
* @collisions: collisions
|
|
* @rx_crc_errors: received packet with crc error
|
|
* @rx_frame_errors: received frame alignment error
|
|
* @rx_alloc_buff_failed: allocate failure of a receive buffer
|
|
* @tx_length_errors: transmit length error
|
|
* @tx_aborted_errors: transmit aborted error
|
|
* @tx_carrier_errors: transmit carrier error
|
|
* @tx_timeout_count: Number of transmit timeout
|
|
* @tx_restart_count: Number of transmit restert
|
|
* @intr_rx_dsc_empty_count: Interrupt count of receive descriptor empty
|
|
* @intr_rx_frame_err_count: Interrupt count of receive frame error
|
|
* @intr_rx_fifo_err_count: Interrupt count of receive FIFO error
|
|
* @intr_rx_dma_err_count: Interrupt count of receive DMA error
|
|
* @intr_tx_fifo_err_count: Interrupt count of transmit FIFO error
|
|
* @intr_tx_dma_err_count: Interrupt count of transmit DMA error
|
|
* @intr_tcpip_err_count: Interrupt count of TCP/IP Accelerator
|
|
*/
|
|
struct pch_gbe_hw_stats {
|
|
u32 rx_packets;
|
|
u32 tx_packets;
|
|
u32 rx_bytes;
|
|
u32 tx_bytes;
|
|
u32 rx_errors;
|
|
u32 tx_errors;
|
|
u32 rx_dropped;
|
|
u32 tx_dropped;
|
|
u32 multicast;
|
|
u32 collisions;
|
|
u32 rx_crc_errors;
|
|
u32 rx_frame_errors;
|
|
u32 rx_alloc_buff_failed;
|
|
u32 tx_length_errors;
|
|
u32 tx_aborted_errors;
|
|
u32 tx_carrier_errors;
|
|
u32 tx_timeout_count;
|
|
u32 tx_restart_count;
|
|
u32 intr_rx_dsc_empty_count;
|
|
u32 intr_rx_frame_err_count;
|
|
u32 intr_rx_fifo_err_count;
|
|
u32 intr_rx_dma_err_count;
|
|
u32 intr_tx_fifo_err_count;
|
|
u32 intr_tx_dma_err_count;
|
|
u32 intr_tcpip_err_count;
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_privdata - PCI Device ID driver data
|
|
* @phy_tx_clk_delay: Bool, configure the PHY TX delay in software
|
|
* @phy_disable_hibernate: Bool, disable PHY hibernation
|
|
* @platform_init: Platform initialization callback, called from
|
|
* probe, prior to PHY initialization.
|
|
*/
|
|
struct pch_gbe_privdata {
|
|
bool phy_tx_clk_delay;
|
|
bool phy_disable_hibernate;
|
|
int (*platform_init)(struct pci_dev *pdev);
|
|
};
|
|
|
|
/**
|
|
* struct pch_gbe_adapter - board specific private data structure
|
|
* @stats_lock: Spinlock structure for status
|
|
* @ethtool_lock: Spinlock structure for ethtool
|
|
* @irq_sem: Semaphore for interrupt
|
|
* @netdev: Pointer of network device structure
|
|
* @pdev: Pointer of pci device structure
|
|
* @polling_netdev: Pointer of polling network device structure
|
|
* @napi: NAPI structure
|
|
* @hw: Pointer of hardware structure
|
|
* @stats: Hardware status
|
|
* @reset_task: Reset task
|
|
* @mii: MII information structure
|
|
* @watchdog_timer: Watchdog timer list
|
|
* @wake_up_evt: Wake up event
|
|
* @config_space: Configuration space
|
|
* @msg_enable: Driver message level
|
|
* @led_status: LED status
|
|
* @tx_ring: Pointer of Tx descriptor ring structure
|
|
* @rx_ring: Pointer of Rx descriptor ring structure
|
|
* @rx_buffer_len: Receive buffer length
|
|
* @tx_queue_len: Transmit queue length
|
|
* @have_msi: PCI MSI mode flag
|
|
* @pch_gbe_privdata: PCI Device ID driver_data
|
|
*/
|
|
|
|
struct pch_gbe_adapter {
|
|
spinlock_t stats_lock;
|
|
spinlock_t ethtool_lock;
|
|
atomic_t irq_sem;
|
|
struct net_device *netdev;
|
|
struct pci_dev *pdev;
|
|
struct net_device *polling_netdev;
|
|
struct napi_struct napi;
|
|
struct pch_gbe_hw hw;
|
|
struct pch_gbe_hw_stats stats;
|
|
struct work_struct reset_task;
|
|
struct mii_if_info mii;
|
|
struct timer_list watchdog_timer;
|
|
u32 wake_up_evt;
|
|
u32 *config_space;
|
|
unsigned long led_status;
|
|
struct pch_gbe_tx_ring *tx_ring;
|
|
struct pch_gbe_rx_ring *rx_ring;
|
|
unsigned long rx_buffer_len;
|
|
unsigned long tx_queue_len;
|
|
bool have_msi;
|
|
bool rx_stop_flag;
|
|
int hwts_tx_en;
|
|
int hwts_rx_en;
|
|
struct pci_dev *ptp_pdev;
|
|
struct pch_gbe_privdata *pdata;
|
|
};
|
|
|
|
#define pch_gbe_hw_to_adapter(hw) container_of(hw, struct pch_gbe_adapter, hw)
|
|
|
|
extern const char pch_driver_version[];
|
|
|
|
/* pch_gbe_main.c */
|
|
int pch_gbe_up(struct pch_gbe_adapter *adapter);
|
|
void pch_gbe_down(struct pch_gbe_adapter *adapter);
|
|
void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
|
|
void pch_gbe_reset(struct pch_gbe_adapter *adapter);
|
|
int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
|
|
struct pch_gbe_tx_ring *txdr);
|
|
int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
|
|
struct pch_gbe_rx_ring *rxdr);
|
|
void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
|
|
struct pch_gbe_tx_ring *tx_ring);
|
|
void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
|
|
struct pch_gbe_rx_ring *rx_ring);
|
|
void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
|
|
u32 pch_ch_control_read(struct pci_dev *pdev);
|
|
void pch_ch_control_write(struct pci_dev *pdev, u32 val);
|
|
u32 pch_ch_event_read(struct pci_dev *pdev);
|
|
void pch_ch_event_write(struct pci_dev *pdev, u32 val);
|
|
u32 pch_src_uuid_lo_read(struct pci_dev *pdev);
|
|
u32 pch_src_uuid_hi_read(struct pci_dev *pdev);
|
|
u64 pch_rx_snap_read(struct pci_dev *pdev);
|
|
u64 pch_tx_snap_read(struct pci_dev *pdev);
|
|
int pch_set_station_address(u8 *addr, struct pci_dev *pdev);
|
|
|
|
/* pch_gbe_param.c */
|
|
void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
|
|
|
|
/* pch_gbe_ethtool.c */
|
|
void pch_gbe_set_ethtool_ops(struct net_device *netdev);
|
|
|
|
/* pch_gbe_mac.c */
|
|
s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
|
|
s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw);
|
|
u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
|
|
u16 data);
|
|
#endif /* _PCH_GBE_H_ */
|