283 lines
6.1 KiB
C
283 lines
6.1 KiB
C
/*
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* linux/arch/arm/mach-clps711x/core.c
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*
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* Core support for the CLPS711x-based machines.
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*
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* Copyright (C) 2001,2011 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <asm/sizes.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/system_misc.h>
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#include <mach/hardware.h>
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static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
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*clk_tint, *clk_spi;
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static unsigned long latch;
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/*
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* This maps the generic CLPS711x registers
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*/
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static struct map_desc clps711x_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)CLPS711X_VIRT_BASE,
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.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
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.length = SZ_1M,
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.type = MT_DEVICE
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}
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};
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void __init clps711x_map_io(void)
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{
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iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
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}
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static void int1_mask(struct irq_data *d)
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{
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u32 intmr1;
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intmr1 = clps_readl(INTMR1);
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intmr1 &= ~(1 << d->irq);
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clps_writel(intmr1, INTMR1);
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}
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static void int1_ack(struct irq_data *d)
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{
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switch (d->irq) {
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case IRQ_CSINT: clps_writel(0, COEOI); break;
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case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
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case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
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case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
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case IRQ_TINT: clps_writel(0, TEOI); break;
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case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
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}
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}
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static void int1_unmask(struct irq_data *d)
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{
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u32 intmr1;
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intmr1 = clps_readl(INTMR1);
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intmr1 |= 1 << d->irq;
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clps_writel(intmr1, INTMR1);
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}
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static struct irq_chip int1_chip = {
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.irq_ack = int1_ack,
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.irq_mask = int1_mask,
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.irq_unmask = int1_unmask,
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};
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static void int2_mask(struct irq_data *d)
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{
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u32 intmr2;
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intmr2 = clps_readl(INTMR2);
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intmr2 &= ~(1 << (d->irq - 16));
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clps_writel(intmr2, INTMR2);
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}
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static void int2_ack(struct irq_data *d)
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{
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switch (d->irq) {
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case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
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}
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}
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static void int2_unmask(struct irq_data *d)
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{
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u32 intmr2;
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intmr2 = clps_readl(INTMR2);
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intmr2 |= 1 << (d->irq - 16);
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clps_writel(intmr2, INTMR2);
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}
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static struct irq_chip int2_chip = {
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.irq_ack = int2_ack,
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.irq_mask = int2_mask,
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.irq_unmask = int2_unmask,
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};
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void __init clps711x_init_irq(void)
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{
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unsigned int i;
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for (i = 0; i < NR_IRQS; i++) {
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if (INT1_IRQS & (1 << i)) {
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irq_set_chip_and_handler(i, &int1_chip,
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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if (INT2_IRQS & (1 << i)) {
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irq_set_chip_and_handler(i, &int2_chip,
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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/*
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* Disable interrupts
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*/
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clps_writel(0, INTMR1);
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clps_writel(0, INTMR2);
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/*
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* Clear down any pending interrupts
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*/
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clps_writel(0, COEOI);
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clps_writel(0, TC1EOI);
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clps_writel(0, TC2EOI);
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clps_writel(0, RTCEOI);
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clps_writel(0, TEOI);
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clps_writel(0, UMSEOI);
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clps_writel(0, SYNCIO);
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clps_writel(0, KBDEOI);
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}
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/*
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* gettimeoffset() returns time since last timer tick, in usecs.
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*
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* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
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* 'tick' is usecs per jiffy.
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*/
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static unsigned long clps711x_gettimeoffset(void)
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{
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unsigned long hwticks;
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hwticks = latch - (clps_readl(TC2D) & 0xffff);
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return (hwticks * (tick_nsec / 1000)) / latch;
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
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{
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timer_tick();
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return IRQ_HANDLED;
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}
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static struct irqaction clps711x_timer_irq = {
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.name = "CLPS711x Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = p720t_timer_interrupt,
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};
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static void add_fixed_clk(struct clk *clk, const char *name, int rate)
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{
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clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
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clk_register_clkdev(clk, name, NULL);
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}
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static void __init clps711x_timer_init(void)
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{
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int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
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u32 tmp;
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osc = 3686400;
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ext = 13000000;
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tmp = clps_readl(PLLR) >> 24;
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if (tmp)
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pll = (osc * tmp) / 2;
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else
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pll = 73728000; /* Default value */
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tmp = clps_readl(SYSFLG2);
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if (tmp & SYSFLG2_CKMODE) {
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cpu = ext;
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bus = cpu;
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spi = 135400;
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} else {
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cpu = pll;
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if (cpu >= 36864000)
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bus = cpu / 2;
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else
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bus = 36864000 / 2;
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spi = cpu / 576;
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}
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uart = bus / 10;
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if (tmp & SYSFLG2_CKMODE) {
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tmp = clps_readl(SYSCON2);
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if (tmp & SYSCON2_OSTB)
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timh = ext / 26;
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else
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timh = 541440;
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} else
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timh = cpu / 144;
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timl = timh / 256;
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/* All clocks are fixed */
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add_fixed_clk(clk_pll, "pll", pll);
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add_fixed_clk(clk_bus, "bus", bus);
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add_fixed_clk(clk_uart, "uart", uart);
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add_fixed_clk(clk_timerl, "timer_lf", timl);
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add_fixed_clk(clk_timerh, "timer_hf", timh);
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add_fixed_clk(clk_tint, "tint", 64);
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add_fixed_clk(clk_spi, "spi", spi);
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pr_info("CPU frequency set at %i Hz.\n", cpu);
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latch = (timh + HZ / 2) / HZ;
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tmp = clps_readl(SYSCON1);
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tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
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clps_writel(tmp, SYSCON1);
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clps_writel(latch - 1, TC2D);
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setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
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}
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struct sys_timer clps711x_timer = {
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.init = clps711x_timer_init,
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.offset = clps711x_gettimeoffset,
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};
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void clps711x_restart(char mode, const char *cmd)
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{
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soft_restart(0);
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}
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static void clps711x_idle(void)
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{
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clps_writel(1, HALT);
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__asm__ __volatile__(
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"mov r0, r0\n\
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mov r0, r0");
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}
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static int __init clps711x_idle_init(void)
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{
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arm_pm_idle = clps711x_idle;
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return 0;
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}
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arch_initcall(clps711x_idle_init);
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