876 lines
20 KiB
C
876 lines
20 KiB
C
/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _CORE_H_
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#define _CORE_H_
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#include <linux/completion.h>
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#include <linux/if_ether.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/uuid.h>
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#include <linux/time.h>
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#include "htt.h"
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#include "htc.h"
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#include "hw.h"
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#include "targaddrs.h"
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#include "wmi.h"
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#include "../ath.h"
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#include "../regd.h"
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#include "../dfs_pattern_detector.h"
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#include "spectral.h"
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#include "thermal.h"
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#include "wow.h"
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#include "swap.h"
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#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
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#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
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#define WO(_f) ((_f##_OFFSET) >> 2)
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#define ATH10K_SCAN_ID 0
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#define WMI_READY_TIMEOUT (5 * HZ)
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#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
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#define ATH10K_CONNECTION_LOSS_HZ (3*HZ)
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#define ATH10K_NUM_CHANS 39
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/* Antenna noise floor */
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#define ATH10K_DEFAULT_NOISE_FLOOR -95
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#define ATH10K_MAX_NUM_MGMT_PENDING 128
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/* number of failed packets (20 packets with 16 sw reties each) */
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#define ATH10K_KICKOUT_THRESHOLD (20 * 16)
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/*
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* Use insanely high numbers to make sure that the firmware implementation
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* won't start, we have the same functionality already in hostapd. Unit
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* is seconds.
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*/
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#define ATH10K_KEEPALIVE_MIN_IDLE 3747
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#define ATH10K_KEEPALIVE_MAX_IDLE 3895
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#define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
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struct ath10k;
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enum ath10k_bus {
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ATH10K_BUS_PCI,
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};
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static inline const char *ath10k_bus_str(enum ath10k_bus bus)
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{
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switch (bus) {
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case ATH10K_BUS_PCI:
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return "pci";
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}
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return "unknown";
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}
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enum ath10k_skb_flags {
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ATH10K_SKB_F_NO_HWCRYPT = BIT(0),
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ATH10K_SKB_F_DTIM_ZERO = BIT(1),
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ATH10K_SKB_F_DELIVER_CAB = BIT(2),
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ATH10K_SKB_F_MGMT = BIT(3),
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ATH10K_SKB_F_QOS = BIT(4),
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};
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struct ath10k_skb_cb {
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dma_addr_t paddr;
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u8 flags;
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u8 eid;
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u16 msdu_id;
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struct ieee80211_vif *vif;
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} __packed;
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struct ath10k_skb_rxcb {
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dma_addr_t paddr;
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struct hlist_node hlist;
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};
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static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
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{
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BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
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IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
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return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
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}
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static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
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{
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BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
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return (struct ath10k_skb_rxcb *)skb->cb;
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}
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#define ATH10K_RXCB_SKB(rxcb) \
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container_of((void *)rxcb, struct sk_buff, cb)
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static inline u32 host_interest_item_address(u32 item_offset)
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{
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return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
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}
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struct ath10k_bmi {
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bool done_sent;
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};
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struct ath10k_mem_chunk {
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void *vaddr;
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dma_addr_t paddr;
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u32 len;
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u32 req_id;
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};
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struct ath10k_wmi {
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enum ath10k_fw_wmi_op_version op_version;
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enum ath10k_htc_ep_id eid;
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struct completion service_ready;
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struct completion unified_ready;
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wait_queue_head_t tx_credits_wq;
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DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
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struct wmi_cmd_map *cmd;
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struct wmi_vdev_param_map *vdev_param;
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struct wmi_pdev_param_map *pdev_param;
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const struct wmi_ops *ops;
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const struct wmi_peer_flags_map *peer_flags;
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u32 num_mem_chunks;
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u32 rx_decap_mode;
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struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
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};
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struct ath10k_fw_stats_peer {
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struct list_head list;
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u8 peer_macaddr[ETH_ALEN];
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u32 peer_rssi;
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u32 peer_tx_rate;
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u32 peer_rx_rate; /* 10x only */
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u32 rx_duration;
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};
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struct ath10k_fw_stats_vdev {
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struct list_head list;
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u32 vdev_id;
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u32 beacon_snr;
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u32 data_snr;
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u32 num_tx_frames[4];
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u32 num_rx_frames;
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u32 num_tx_frames_retries[4];
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u32 num_tx_frames_failures[4];
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u32 num_rts_fail;
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u32 num_rts_success;
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u32 num_rx_err;
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u32 num_rx_discard;
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u32 num_tx_not_acked;
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u32 tx_rate_history[10];
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u32 beacon_rssi_history[10];
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};
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struct ath10k_fw_stats_pdev {
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struct list_head list;
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/* PDEV stats */
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s32 ch_noise_floor;
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u32 tx_frame_count;
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u32 rx_frame_count;
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u32 rx_clear_count;
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u32 cycle_count;
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u32 phy_err_count;
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u32 chan_tx_power;
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u32 ack_rx_bad;
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u32 rts_bad;
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u32 rts_good;
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u32 fcs_bad;
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u32 no_beacons;
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u32 mib_int_count;
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/* PDEV TX stats */
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s32 comp_queued;
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s32 comp_delivered;
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s32 msdu_enqued;
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s32 mpdu_enqued;
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s32 wmm_drop;
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s32 local_enqued;
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s32 local_freed;
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s32 hw_queued;
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s32 hw_reaped;
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s32 underrun;
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u32 hw_paused;
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s32 tx_abort;
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s32 mpdus_requed;
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u32 tx_ko;
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u32 data_rc;
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u32 self_triggers;
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u32 sw_retry_failure;
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u32 illgl_rate_phy_err;
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u32 pdev_cont_xretry;
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u32 pdev_tx_timeout;
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u32 pdev_resets;
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u32 phy_underrun;
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u32 txop_ovf;
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u32 seq_posted;
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u32 seq_failed_queueing;
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u32 seq_completed;
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u32 seq_restarted;
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u32 mu_seq_posted;
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u32 mpdus_sw_flush;
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u32 mpdus_hw_filter;
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u32 mpdus_truncated;
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u32 mpdus_ack_failed;
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u32 mpdus_expired;
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/* PDEV RX stats */
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s32 mid_ppdu_route_change;
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s32 status_rcvd;
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s32 r0_frags;
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s32 r1_frags;
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s32 r2_frags;
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s32 r3_frags;
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s32 htt_msdus;
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s32 htt_mpdus;
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s32 loc_msdus;
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s32 loc_mpdus;
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s32 oversize_amsdu;
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s32 phy_errs;
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s32 phy_err_drop;
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s32 mpdu_errs;
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s32 rx_ovfl_errs;
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};
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struct ath10k_fw_stats {
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struct list_head pdevs;
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struct list_head vdevs;
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struct list_head peers;
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};
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#define ATH10K_TPC_TABLE_TYPE_FLAG 1
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#define ATH10K_TPC_PREAM_TABLE_END 0xFFFF
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struct ath10k_tpc_table {
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u32 pream_idx[WMI_TPC_RATE_MAX];
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u8 rate_code[WMI_TPC_RATE_MAX];
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char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
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};
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struct ath10k_tpc_stats {
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u32 reg_domain;
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u32 chan_freq;
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u32 phy_mode;
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u32 twice_antenna_reduction;
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u32 twice_max_rd_power;
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s32 twice_antenna_gain;
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u32 power_limit;
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u32 num_tx_chain;
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u32 ctl;
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u32 rate_max;
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u8 flag[WMI_TPC_FLAG];
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struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
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};
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struct ath10k_dfs_stats {
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u32 phy_errors;
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u32 pulses_total;
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u32 pulses_detected;
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u32 pulses_discarded;
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u32 radar_detected;
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};
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#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
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struct ath10k_peer {
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struct list_head list;
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int vdev_id;
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u8 addr[ETH_ALEN];
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DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
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/* protected by ar->data_lock */
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struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
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};
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struct ath10k_sta {
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struct ath10k_vif *arvif;
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/* the following are protected by ar->data_lock */
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u32 changed; /* IEEE80211_RC_* */
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u32 bw;
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u32 nss;
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u32 smps;
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struct work_struct update_wk;
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#ifdef CONFIG_MAC80211_DEBUGFS
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/* protected by conf_mutex */
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bool aggr_mode;
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#endif
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};
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#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
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enum ath10k_beacon_state {
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ATH10K_BEACON_SCHEDULED = 0,
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ATH10K_BEACON_SENDING,
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ATH10K_BEACON_SENT,
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};
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struct ath10k_vif {
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struct list_head list;
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u32 vdev_id;
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enum wmi_vdev_type vdev_type;
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enum wmi_vdev_subtype vdev_subtype;
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u32 beacon_interval;
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u32 dtim_period;
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struct sk_buff *beacon;
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/* protected by data_lock */
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enum ath10k_beacon_state beacon_state;
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void *beacon_buf;
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dma_addr_t beacon_paddr;
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unsigned long tx_paused; /* arbitrary values defined by target */
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struct ath10k *ar;
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struct ieee80211_vif *vif;
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bool is_started;
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bool is_up;
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bool spectral_enabled;
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bool ps;
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u32 aid;
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u8 bssid[ETH_ALEN];
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struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
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s8 def_wep_key_idx;
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u16 tx_seq_no;
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union {
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struct {
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u32 uapsd;
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} sta;
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struct {
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/* 512 stations */
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u8 tim_bitmap[64];
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u8 tim_len;
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u32 ssid_len;
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u8 ssid[IEEE80211_MAX_SSID_LEN];
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bool hidden_ssid;
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/* P2P_IE with NoA attribute for P2P_GO case */
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u32 noa_len;
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u8 *noa_data;
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} ap;
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} u;
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bool use_cts_prot;
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bool nohwcrypt;
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int num_legacy_stations;
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int txpower;
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struct wmi_wmm_params_all_arg wmm_params;
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struct work_struct ap_csa_work;
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struct delayed_work connection_loss_work;
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struct cfg80211_bitrate_mask bitrate_mask;
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};
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struct ath10k_vif_iter {
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u32 vdev_id;
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struct ath10k_vif *arvif;
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};
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/* used for crash-dump storage, protected by data-lock */
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struct ath10k_fw_crash_data {
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bool crashed_since_read;
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uuid_le uuid;
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struct timespec timestamp;
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__le32 registers[REG_DUMP_COUNT_QCA988X];
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};
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struct ath10k_debug {
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struct dentry *debugfs_phy;
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struct ath10k_fw_stats fw_stats;
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struct completion fw_stats_complete;
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bool fw_stats_done;
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unsigned long htt_stats_mask;
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struct delayed_work htt_stats_dwork;
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struct ath10k_dfs_stats dfs_stats;
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struct ath_dfs_pool_stats dfs_pool_stats;
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/* used for tpc-dump storage, protected by data-lock */
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struct ath10k_tpc_stats *tpc_stats;
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struct completion tpc_complete;
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/* protected by conf_mutex */
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u32 fw_dbglog_mask;
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u32 fw_dbglog_level;
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u32 pktlog_filter;
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u32 reg_addr;
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u32 nf_cal_period;
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struct ath10k_fw_crash_data *fw_crash_data;
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};
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enum ath10k_state {
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ATH10K_STATE_OFF = 0,
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ATH10K_STATE_ON,
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/* When doing firmware recovery the device is first powered down.
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* mac80211 is supposed to call in to start() hook later on. It is
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* however possible that driver unloading and firmware crash overlap.
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* mac80211 can wait on conf_mutex in stop() while the device is
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* stopped in ath10k_core_restart() work holding conf_mutex. The state
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* RESTARTED means that the device is up and mac80211 has started hw
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* reconfiguration. Once mac80211 is done with the reconfiguration we
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* set the state to STATE_ON in reconfig_complete(). */
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ATH10K_STATE_RESTARTING,
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ATH10K_STATE_RESTARTED,
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/* The device has crashed while restarting hw. This state is like ON
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* but commands are blocked in HTC and -ECOMM response is given. This
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* prevents completion timeouts and makes the driver more responsive to
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* userspace commands. This is also prevents recursive recovery. */
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ATH10K_STATE_WEDGED,
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/* factory tests */
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ATH10K_STATE_UTF,
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};
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enum ath10k_firmware_mode {
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/* the default mode, standard 802.11 functionality */
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ATH10K_FIRMWARE_MODE_NORMAL,
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/* factory tests etc */
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ATH10K_FIRMWARE_MODE_UTF,
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};
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enum ath10k_fw_features {
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/* wmi_mgmt_rx_hdr contains extra RSSI information */
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ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
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/* Firmware from 10X branch. Deprecated, don't use in new code. */
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ATH10K_FW_FEATURE_WMI_10X = 1,
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/* firmware support tx frame management over WMI, otherwise it's HTT */
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ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
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/* Firmware does not support P2P */
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ATH10K_FW_FEATURE_NO_P2P = 3,
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/* Firmware 10.2 feature bit. The ATH10K_FW_FEATURE_WMI_10X feature
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* bit is required to be set as well. Deprecated, don't use in new
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* code.
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*/
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ATH10K_FW_FEATURE_WMI_10_2 = 4,
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/* Some firmware revisions lack proper multi-interface client powersave
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* implementation. Enabling PS could result in connection drops,
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* traffic stalls, etc.
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*/
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ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
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/* Some firmware revisions have an incomplete WoWLAN implementation
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* despite WMI service bit being advertised. This feature flag is used
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* to distinguish whether WoWLAN is really supported or not.
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*/
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ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6,
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/* Don't trust error code from otp.bin */
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ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7,
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/* Some firmware revisions pad 4th hw address to 4 byte boundary making
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* it 8 bytes long in Native Wifi Rx decap.
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*/
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ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8,
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/* Firmware supports bypassing PLL setting on init. */
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ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9,
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/* Raw mode support. If supported, FW supports receiving and trasmitting
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* frames in raw mode.
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*/
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ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10,
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/* Firmware Supports Adaptive CCA*/
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ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11,
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/* Firmware supports management frame protection */
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ATH10K_FW_FEATURE_MFP_SUPPORT = 12,
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|
|
|
/* keep last */
|
|
ATH10K_FW_FEATURE_COUNT,
|
|
};
|
|
|
|
enum ath10k_dev_flags {
|
|
/* Indicates that ath10k device is during CAC phase of DFS */
|
|
ATH10K_CAC_RUNNING,
|
|
ATH10K_FLAG_CORE_REGISTERED,
|
|
|
|
/* Device has crashed and needs to restart. This indicates any pending
|
|
* waiters should immediately cancel instead of waiting for a time out.
|
|
*/
|
|
ATH10K_FLAG_CRASH_FLUSH,
|
|
|
|
/* Use Raw mode instead of native WiFi Tx/Rx encap mode.
|
|
* Raw mode supports both hardware and software crypto. Native WiFi only
|
|
* supports hardware crypto.
|
|
*/
|
|
ATH10K_FLAG_RAW_MODE,
|
|
|
|
/* Disable HW crypto engine */
|
|
ATH10K_FLAG_HW_CRYPTO_DISABLED,
|
|
|
|
/* Bluetooth coexistance enabled */
|
|
ATH10K_FLAG_BTCOEX,
|
|
};
|
|
|
|
enum ath10k_cal_mode {
|
|
ATH10K_CAL_MODE_FILE,
|
|
ATH10K_CAL_MODE_OTP,
|
|
ATH10K_CAL_MODE_DT,
|
|
};
|
|
|
|
enum ath10k_crypt_mode {
|
|
/* Only use hardware crypto engine */
|
|
ATH10K_CRYPT_MODE_HW,
|
|
/* Only use software crypto engine */
|
|
ATH10K_CRYPT_MODE_SW,
|
|
};
|
|
|
|
static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
|
|
{
|
|
switch (mode) {
|
|
case ATH10K_CAL_MODE_FILE:
|
|
return "file";
|
|
case ATH10K_CAL_MODE_OTP:
|
|
return "otp";
|
|
case ATH10K_CAL_MODE_DT:
|
|
return "dt";
|
|
}
|
|
|
|
return "unknown";
|
|
}
|
|
|
|
enum ath10k_scan_state {
|
|
ATH10K_SCAN_IDLE,
|
|
ATH10K_SCAN_STARTING,
|
|
ATH10K_SCAN_RUNNING,
|
|
ATH10K_SCAN_ABORTING,
|
|
};
|
|
|
|
static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
|
|
{
|
|
switch (state) {
|
|
case ATH10K_SCAN_IDLE:
|
|
return "idle";
|
|
case ATH10K_SCAN_STARTING:
|
|
return "starting";
|
|
case ATH10K_SCAN_RUNNING:
|
|
return "running";
|
|
case ATH10K_SCAN_ABORTING:
|
|
return "aborting";
|
|
}
|
|
|
|
return "unknown";
|
|
}
|
|
|
|
enum ath10k_tx_pause_reason {
|
|
ATH10K_TX_PAUSE_Q_FULL,
|
|
ATH10K_TX_PAUSE_MAX,
|
|
};
|
|
|
|
struct ath10k {
|
|
struct ath_common ath_common;
|
|
struct ieee80211_hw *hw;
|
|
struct device *dev;
|
|
u8 mac_addr[ETH_ALEN];
|
|
|
|
enum ath10k_hw_rev hw_rev;
|
|
u16 dev_id;
|
|
u32 chip_id;
|
|
u32 target_version;
|
|
u8 fw_version_major;
|
|
u32 fw_version_minor;
|
|
u16 fw_version_release;
|
|
u16 fw_version_build;
|
|
u32 fw_stats_req_mask;
|
|
u32 phy_capability;
|
|
u32 hw_min_tx_power;
|
|
u32 hw_max_tx_power;
|
|
u32 ht_cap_info;
|
|
u32 vht_cap_info;
|
|
u32 num_rf_chains;
|
|
u32 max_spatial_stream;
|
|
/* protected by conf_mutex */
|
|
bool ani_enabled;
|
|
|
|
DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
|
|
|
|
bool p2p;
|
|
|
|
struct {
|
|
enum ath10k_bus bus;
|
|
const struct ath10k_hif_ops *ops;
|
|
} hif;
|
|
|
|
struct completion target_suspend;
|
|
|
|
const struct ath10k_hw_regs *regs;
|
|
const struct ath10k_hw_values *hw_values;
|
|
struct ath10k_bmi bmi;
|
|
struct ath10k_wmi wmi;
|
|
struct ath10k_htc htc;
|
|
struct ath10k_htt htt;
|
|
|
|
struct ath10k_hw_params {
|
|
u32 id;
|
|
u16 dev_id;
|
|
const char *name;
|
|
u32 patch_load_addr;
|
|
int uart_pin;
|
|
u32 otp_exe_param;
|
|
|
|
/* This is true if given HW chip has a quirky Cycle Counter
|
|
* wraparound which resets to 0x7fffffff instead of 0. All
|
|
* other CC related counters (e.g. Rx Clear Count) are divided
|
|
* by 2 so they never wraparound themselves.
|
|
*/
|
|
bool has_shifted_cc_wraparound;
|
|
|
|
/* Some of chip expects fragment descriptor to be continuous
|
|
* memory for any TX operation. Set continuous_frag_desc flag
|
|
* for the hardware which have such requirement.
|
|
*/
|
|
bool continuous_frag_desc;
|
|
|
|
u32 channel_counters_freq_hz;
|
|
|
|
/* Mgmt tx descriptors threshold for limiting probe response
|
|
* frames.
|
|
*/
|
|
u32 max_probe_resp_desc_thres;
|
|
|
|
/* The padding bytes's location is different on various chips */
|
|
enum ath10k_hw_4addr_pad hw_4addr_pad;
|
|
|
|
struct ath10k_hw_params_fw {
|
|
const char *dir;
|
|
const char *fw;
|
|
const char *otp;
|
|
const char *board;
|
|
size_t board_size;
|
|
size_t board_ext_size;
|
|
} fw;
|
|
} hw_params;
|
|
|
|
const struct firmware *board;
|
|
const void *board_data;
|
|
size_t board_len;
|
|
|
|
const struct firmware *otp;
|
|
const void *otp_data;
|
|
size_t otp_len;
|
|
|
|
const struct firmware *firmware;
|
|
const void *firmware_data;
|
|
size_t firmware_len;
|
|
|
|
const struct firmware *cal_file;
|
|
|
|
struct {
|
|
const void *firmware_codeswap_data;
|
|
size_t firmware_codeswap_len;
|
|
struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info;
|
|
} swap;
|
|
|
|
struct {
|
|
u32 vendor;
|
|
u32 device;
|
|
u32 subsystem_vendor;
|
|
u32 subsystem_device;
|
|
|
|
bool bmi_ids_valid;
|
|
u8 bmi_board_id;
|
|
u8 bmi_chip_id;
|
|
} id;
|
|
|
|
int fw_api;
|
|
int bd_api;
|
|
enum ath10k_cal_mode cal_mode;
|
|
|
|
struct {
|
|
struct completion started;
|
|
struct completion completed;
|
|
struct completion on_channel;
|
|
struct delayed_work timeout;
|
|
enum ath10k_scan_state state;
|
|
bool is_roc;
|
|
int vdev_id;
|
|
int roc_freq;
|
|
bool roc_notify;
|
|
} scan;
|
|
|
|
struct {
|
|
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
|
} mac;
|
|
|
|
/* should never be NULL; needed for regular htt rx */
|
|
struct ieee80211_channel *rx_channel;
|
|
|
|
/* valid during scan; needed for mgmt rx during scan */
|
|
struct ieee80211_channel *scan_channel;
|
|
|
|
/* current operating channel definition */
|
|
struct cfg80211_chan_def chandef;
|
|
|
|
unsigned long long free_vdev_map;
|
|
struct ath10k_vif *monitor_arvif;
|
|
bool monitor;
|
|
int monitor_vdev_id;
|
|
bool monitor_started;
|
|
unsigned int filter_flags;
|
|
unsigned long dev_flags;
|
|
bool dfs_block_radar_events;
|
|
|
|
/* protected by conf_mutex */
|
|
bool radar_enabled;
|
|
int num_started_vdevs;
|
|
|
|
/* Protected by conf-mutex */
|
|
u8 cfg_tx_chainmask;
|
|
u8 cfg_rx_chainmask;
|
|
|
|
struct completion install_key_done;
|
|
|
|
struct completion vdev_setup_done;
|
|
|
|
struct workqueue_struct *workqueue;
|
|
/* Auxiliary workqueue */
|
|
struct workqueue_struct *workqueue_aux;
|
|
|
|
/* prevents concurrent FW reconfiguration */
|
|
struct mutex conf_mutex;
|
|
|
|
/* protects shared structure data */
|
|
spinlock_t data_lock;
|
|
|
|
struct list_head arvifs;
|
|
struct list_head peers;
|
|
wait_queue_head_t peer_mapping_wq;
|
|
|
|
/* protected by conf_mutex */
|
|
int num_peers;
|
|
int num_stations;
|
|
|
|
int max_num_peers;
|
|
int max_num_stations;
|
|
int max_num_vdevs;
|
|
int max_num_tdls_vdevs;
|
|
int num_active_peers;
|
|
int num_tids;
|
|
|
|
struct work_struct svc_rdy_work;
|
|
struct sk_buff *svc_rdy_skb;
|
|
|
|
struct work_struct offchan_tx_work;
|
|
struct sk_buff_head offchan_tx_queue;
|
|
struct completion offchan_tx_completed;
|
|
struct sk_buff *offchan_tx_skb;
|
|
|
|
struct work_struct wmi_mgmt_tx_work;
|
|
struct sk_buff_head wmi_mgmt_tx_queue;
|
|
|
|
enum ath10k_state state;
|
|
|
|
struct work_struct register_work;
|
|
struct work_struct restart_work;
|
|
|
|
/* cycle count is reported twice for each visited channel during scan.
|
|
* access protected by data_lock */
|
|
u32 survey_last_rx_clear_count;
|
|
u32 survey_last_cycle_count;
|
|
struct survey_info survey[ATH10K_NUM_CHANS];
|
|
|
|
/* Channel info events are expected to come in pairs without and with
|
|
* COMPLETE flag set respectively for each channel visit during scan.
|
|
*
|
|
* However there are deviations from this rule. This flag is used to
|
|
* avoid reporting garbage data.
|
|
*/
|
|
bool ch_info_can_report_survey;
|
|
|
|
struct dfs_pattern_detector *dfs_detector;
|
|
|
|
unsigned long tx_paused; /* see ATH10K_TX_PAUSE_ */
|
|
|
|
#ifdef CONFIG_ATH10K_DEBUGFS
|
|
struct ath10k_debug debug;
|
|
#endif
|
|
|
|
struct {
|
|
/* relay(fs) channel for spectral scan */
|
|
struct rchan *rfs_chan_spec_scan;
|
|
|
|
/* spectral_mode and spec_config are protected by conf_mutex */
|
|
enum ath10k_spectral_mode mode;
|
|
struct ath10k_spec_scan config;
|
|
} spectral;
|
|
|
|
struct {
|
|
/* protected by conf_mutex */
|
|
const struct firmware *utf;
|
|
char utf_version[32];
|
|
const void *utf_firmware_data;
|
|
size_t utf_firmware_len;
|
|
DECLARE_BITMAP(orig_fw_features, ATH10K_FW_FEATURE_COUNT);
|
|
enum ath10k_fw_wmi_op_version orig_wmi_op_version;
|
|
enum ath10k_fw_wmi_op_version op_version;
|
|
/* protected by data_lock */
|
|
bool utf_monitor;
|
|
} testmode;
|
|
|
|
struct {
|
|
/* protected by data_lock */
|
|
u32 fw_crash_counter;
|
|
u32 fw_warm_reset_counter;
|
|
u32 fw_cold_reset_counter;
|
|
} stats;
|
|
|
|
struct ath10k_thermal thermal;
|
|
struct ath10k_wow wow;
|
|
|
|
/* must be last */
|
|
u8 drv_priv[0] __aligned(sizeof(void *));
|
|
};
|
|
|
|
struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
|
|
enum ath10k_bus bus,
|
|
enum ath10k_hw_rev hw_rev,
|
|
const struct ath10k_hif_ops *hif_ops);
|
|
void ath10k_core_destroy(struct ath10k *ar);
|
|
void ath10k_core_get_fw_features_str(struct ath10k *ar,
|
|
char *buf,
|
|
size_t max_len);
|
|
|
|
int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode);
|
|
int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
|
|
void ath10k_core_stop(struct ath10k *ar);
|
|
int ath10k_core_register(struct ath10k *ar, u32 chip_id);
|
|
void ath10k_core_unregister(struct ath10k *ar);
|
|
|
|
#endif /* _CORE_H_ */
|