410 lines
10 KiB
C
410 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "dcss-dev.h"
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#define DCSS_DTG_TC_CONTROL_STATUS 0x00
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#define CH3_EN BIT(0)
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#define CH2_EN BIT(1)
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#define CH1_EN BIT(2)
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#define OVL_DATA_MODE BIT(3)
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#define BLENDER_VIDEO_ALPHA_SEL BIT(7)
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#define DTG_START BIT(8)
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#define DBY_MODE_EN BIT(9)
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#define CH1_ALPHA_SEL BIT(10)
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#define CSS_PIX_COMP_SWAP_POS 12
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#define CSS_PIX_COMP_SWAP_MASK GENMASK(14, 12)
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#define DEFAULT_FG_ALPHA_POS 24
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#define DEFAULT_FG_ALPHA_MASK GENMASK(31, 24)
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#define DCSS_DTG_TC_DTG 0x04
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#define DCSS_DTG_TC_DISP_TOP 0x08
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#define DCSS_DTG_TC_DISP_BOT 0x0C
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#define DCSS_DTG_TC_CH1_TOP 0x10
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#define DCSS_DTG_TC_CH1_BOT 0x14
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#define DCSS_DTG_TC_CH2_TOP 0x18
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#define DCSS_DTG_TC_CH2_BOT 0x1C
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#define DCSS_DTG_TC_CH3_TOP 0x20
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#define DCSS_DTG_TC_CH3_BOT 0x24
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#define TC_X_POS 0
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#define TC_X_MASK GENMASK(12, 0)
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#define TC_Y_POS 16
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#define TC_Y_MASK GENMASK(28, 16)
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#define DCSS_DTG_TC_CTXLD 0x28
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#define TC_CTXLD_DB_Y_POS 0
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#define TC_CTXLD_DB_Y_MASK GENMASK(12, 0)
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#define TC_CTXLD_SB_Y_POS 16
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#define TC_CTXLD_SB_Y_MASK GENMASK(28, 16)
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#define DCSS_DTG_TC_CH1_BKRND 0x2C
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#define DCSS_DTG_TC_CH2_BKRND 0x30
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#define BKRND_R_Y_COMP_POS 20
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#define BKRND_R_Y_COMP_MASK GENMASK(29, 20)
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#define BKRND_G_U_COMP_POS 10
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#define BKRND_G_U_COMP_MASK GENMASK(19, 10)
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#define BKRND_B_V_COMP_POS 0
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#define BKRND_B_V_COMP_MASK GENMASK(9, 0)
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#define DCSS_DTG_BLENDER_DBY_RANGEINV 0x38
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#define DCSS_DTG_BLENDER_DBY_RANGEMIN 0x3C
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#define DCSS_DTG_BLENDER_DBY_BDP 0x40
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#define DCSS_DTG_BLENDER_BKRND_I 0x44
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#define DCSS_DTG_BLENDER_BKRND_P 0x48
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#define DCSS_DTG_BLENDER_BKRND_T 0x4C
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#define DCSS_DTG_LINE0_INT 0x50
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#define DCSS_DTG_LINE1_INT 0x54
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#define DCSS_DTG_BG_ALPHA_DEFAULT 0x58
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#define DCSS_DTG_INT_STATUS 0x5C
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#define DCSS_DTG_INT_CONTROL 0x60
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#define DCSS_DTG_TC_CH3_BKRND 0x64
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#define DCSS_DTG_INT_MASK 0x68
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#define LINE0_IRQ BIT(0)
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#define LINE1_IRQ BIT(1)
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#define LINE2_IRQ BIT(2)
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#define LINE3_IRQ BIT(3)
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#define DCSS_DTG_LINE2_INT 0x6C
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#define DCSS_DTG_LINE3_INT 0x70
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#define DCSS_DTG_DBY_OL 0x74
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#define DCSS_DTG_DBY_BL 0x78
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#define DCSS_DTG_DBY_EL 0x7C
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struct dcss_dtg {
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struct device *dev;
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struct dcss_ctxld *ctxld;
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void __iomem *base_reg;
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u32 base_ofs;
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u32 ctx_id;
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bool in_use;
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u32 dis_ulc_x;
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u32 dis_ulc_y;
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u32 control_status;
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u32 alpha;
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u32 alpha_cfg;
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int ctxld_kick_irq;
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bool ctxld_kick_irq_en;
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};
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static void dcss_dtg_write(struct dcss_dtg *dtg, u32 val, u32 ofs)
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{
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if (!dtg->in_use)
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dcss_writel(val, dtg->base_reg + ofs);
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dcss_ctxld_write(dtg->ctxld, dtg->ctx_id,
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val, dtg->base_ofs + ofs);
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}
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static irqreturn_t dcss_dtg_irq_handler(int irq, void *data)
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{
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struct dcss_dtg *dtg = data;
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u32 status;
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status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
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if (!(status & LINE0_IRQ))
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return IRQ_NONE;
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dcss_ctxld_kick(dtg->ctxld);
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dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);
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return IRQ_HANDLED;
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}
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static int dcss_dtg_irq_config(struct dcss_dtg *dtg,
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struct platform_device *pdev)
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{
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int ret;
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dtg->ctxld_kick_irq = platform_get_irq_byname(pdev, "ctxld_kick");
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if (dtg->ctxld_kick_irq < 0)
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return dtg->ctxld_kick_irq;
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dcss_update(0, LINE0_IRQ | LINE1_IRQ,
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dtg->base_reg + DCSS_DTG_INT_MASK);
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ret = request_irq(dtg->ctxld_kick_irq, dcss_dtg_irq_handler,
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0, "dcss_ctxld_kick", dtg);
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if (ret) {
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dev_err(dtg->dev, "dtg: irq request failed.\n");
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return ret;
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}
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disable_irq(dtg->ctxld_kick_irq);
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dtg->ctxld_kick_irq_en = false;
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return 0;
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}
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int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base)
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{
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int ret = 0;
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struct dcss_dtg *dtg;
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dtg = kzalloc(sizeof(*dtg), GFP_KERNEL);
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if (!dtg)
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return -ENOMEM;
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dcss->dtg = dtg;
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dtg->dev = dcss->dev;
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dtg->ctxld = dcss->ctxld;
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dtg->base_reg = ioremap(dtg_base, SZ_4K);
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if (!dtg->base_reg) {
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dev_err(dcss->dev, "dtg: unable to remap dtg base\n");
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ret = -ENOMEM;
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goto err_ioremap;
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}
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dtg->base_ofs = dtg_base;
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dtg->ctx_id = CTX_DB;
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dtg->alpha = 255;
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dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL |
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((dtg->alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK);
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ret = dcss_dtg_irq_config(dtg, to_platform_device(dcss->dev));
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if (ret)
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goto err_irq;
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return 0;
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err_irq:
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iounmap(dtg->base_reg);
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err_ioremap:
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kfree(dtg);
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return ret;
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}
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void dcss_dtg_exit(struct dcss_dtg *dtg)
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{
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free_irq(dtg->ctxld_kick_irq, dtg);
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if (dtg->base_reg)
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iounmap(dtg->base_reg);
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kfree(dtg);
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}
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void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm)
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{
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struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dtg->dev);
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u16 dtg_lrc_x, dtg_lrc_y;
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u16 dis_ulc_x, dis_ulc_y;
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u16 dis_lrc_x, dis_lrc_y;
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u32 sb_ctxld_trig, db_ctxld_trig;
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u32 pixclock = vm->pixelclock;
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u32 actual_clk;
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dtg_lrc_x = vm->hfront_porch + vm->hback_porch + vm->hsync_len +
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vm->hactive - 1;
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dtg_lrc_y = vm->vfront_porch + vm->vback_porch + vm->vsync_len +
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vm->vactive - 1;
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dis_ulc_x = vm->hsync_len + vm->hback_porch - 1;
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dis_ulc_y = vm->vsync_len + vm->vfront_porch + vm->vback_porch - 1;
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dis_lrc_x = vm->hsync_len + vm->hback_porch + vm->hactive - 1;
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dis_lrc_y = vm->vsync_len + vm->vfront_porch + vm->vback_porch +
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vm->vactive - 1;
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clk_disable_unprepare(dcss->pix_clk);
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clk_set_rate(dcss->pix_clk, vm->pixelclock);
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clk_prepare_enable(dcss->pix_clk);
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actual_clk = clk_get_rate(dcss->pix_clk);
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if (pixclock != actual_clk) {
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dev_info(dtg->dev,
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"Pixel clock set to %u kHz instead of %u kHz.\n",
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(actual_clk / 1000), (pixclock / 1000));
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}
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dcss_dtg_write(dtg, ((dtg_lrc_y << TC_Y_POS) | dtg_lrc_x),
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DCSS_DTG_TC_DTG);
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dcss_dtg_write(dtg, ((dis_ulc_y << TC_Y_POS) | dis_ulc_x),
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DCSS_DTG_TC_DISP_TOP);
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dcss_dtg_write(dtg, ((dis_lrc_y << TC_Y_POS) | dis_lrc_x),
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DCSS_DTG_TC_DISP_BOT);
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dtg->dis_ulc_x = dis_ulc_x;
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dtg->dis_ulc_y = dis_ulc_y;
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sb_ctxld_trig = ((0 * dis_lrc_y / 100) << TC_CTXLD_SB_Y_POS) &
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TC_CTXLD_SB_Y_MASK;
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db_ctxld_trig = ((99 * dis_lrc_y / 100) << TC_CTXLD_DB_Y_POS) &
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TC_CTXLD_DB_Y_MASK;
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dcss_dtg_write(dtg, sb_ctxld_trig | db_ctxld_trig, DCSS_DTG_TC_CTXLD);
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/* vblank trigger */
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dcss_dtg_write(dtg, 0, DCSS_DTG_LINE1_INT);
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/* CTXLD trigger */
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dcss_dtg_write(dtg, ((90 * dis_lrc_y) / 100) << 16, DCSS_DTG_LINE0_INT);
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}
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void dcss_dtg_plane_pos_set(struct dcss_dtg *dtg, int ch_num,
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int px, int py, int pw, int ph)
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{
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u16 p_ulc_x, p_ulc_y;
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u16 p_lrc_x, p_lrc_y;
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p_ulc_x = dtg->dis_ulc_x + px;
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p_ulc_y = dtg->dis_ulc_y + py;
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p_lrc_x = p_ulc_x + pw;
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p_lrc_y = p_ulc_y + ph;
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if (!px && !py && !pw && !ph) {
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dcss_dtg_write(dtg, 0, DCSS_DTG_TC_CH1_TOP + 0x8 * ch_num);
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dcss_dtg_write(dtg, 0, DCSS_DTG_TC_CH1_BOT + 0x8 * ch_num);
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} else {
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dcss_dtg_write(dtg, ((p_ulc_y << TC_Y_POS) | p_ulc_x),
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DCSS_DTG_TC_CH1_TOP + 0x8 * ch_num);
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dcss_dtg_write(dtg, ((p_lrc_y << TC_Y_POS) | p_lrc_x),
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DCSS_DTG_TC_CH1_BOT + 0x8 * ch_num);
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}
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}
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bool dcss_dtg_global_alpha_changed(struct dcss_dtg *dtg, int ch_num, int alpha)
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{
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if (ch_num)
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return false;
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return alpha != dtg->alpha;
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}
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void dcss_dtg_plane_alpha_set(struct dcss_dtg *dtg, int ch_num,
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const struct drm_format_info *format, int alpha)
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{
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/* we care about alpha only when channel 0 is concerned */
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if (ch_num)
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return;
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/*
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* Use global alpha if pixel format does not have alpha channel or the
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* user explicitly chose to use global alpha (i.e. alpha is not OPAQUE).
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*/
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if (!format->has_alpha || alpha != 255)
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dtg->alpha_cfg = (alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK;
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else /* use per-pixel alpha otherwise */
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dtg->alpha_cfg = CH1_ALPHA_SEL;
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dtg->alpha = alpha;
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}
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void dcss_dtg_css_set(struct dcss_dtg *dtg)
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{
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dtg->control_status |=
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(0x5 << CSS_PIX_COMP_SWAP_POS) & CSS_PIX_COMP_SWAP_MASK;
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}
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void dcss_dtg_enable(struct dcss_dtg *dtg)
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{
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dtg->control_status |= DTG_START;
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dtg->control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK);
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dtg->control_status |= dtg->alpha_cfg;
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dcss_dtg_write(dtg, dtg->control_status, DCSS_DTG_TC_CONTROL_STATUS);
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dtg->in_use = true;
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}
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void dcss_dtg_shutoff(struct dcss_dtg *dtg)
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{
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dtg->control_status &= ~DTG_START;
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dcss_writel(dtg->control_status,
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dtg->base_reg + DCSS_DTG_TC_CONTROL_STATUS);
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dtg->in_use = false;
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}
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bool dcss_dtg_is_enabled(struct dcss_dtg *dtg)
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{
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return dtg->in_use;
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}
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void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en)
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{
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u32 ch_en_map[] = {CH1_EN, CH2_EN, CH3_EN};
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u32 control_status;
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control_status = dtg->control_status & ~ch_en_map[ch_num];
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control_status |= en ? ch_en_map[ch_num] : 0;
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control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK);
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control_status |= dtg->alpha_cfg;
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if (dtg->control_status != control_status)
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dcss_dtg_write(dtg, control_status, DCSS_DTG_TC_CONTROL_STATUS);
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dtg->control_status = control_status;
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}
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void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en)
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{
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u32 status;
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u32 mask = en ? LINE1_IRQ : 0;
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if (en) {
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status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
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dcss_writel(status & LINE1_IRQ,
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dtg->base_reg + DCSS_DTG_INT_CONTROL);
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}
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dcss_update(mask, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);
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}
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void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en)
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{
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u32 status;
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u32 mask = en ? LINE0_IRQ : 0;
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if (en) {
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status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
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if (!dtg->ctxld_kick_irq_en) {
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dcss_writel(status & LINE0_IRQ,
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dtg->base_reg + DCSS_DTG_INT_CONTROL);
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enable_irq(dtg->ctxld_kick_irq);
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dtg->ctxld_kick_irq_en = true;
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dcss_update(mask, LINE0_IRQ,
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dtg->base_reg + DCSS_DTG_INT_MASK);
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}
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return;
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}
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if (!dtg->ctxld_kick_irq_en)
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return;
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disable_irq_nosync(dtg->ctxld_kick_irq);
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dtg->ctxld_kick_irq_en = false;
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dcss_update(mask, LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);
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}
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void dcss_dtg_vblank_irq_clear(struct dcss_dtg *dtg)
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{
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dcss_update(LINE1_IRQ, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);
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}
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bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg)
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{
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return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ);
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}
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