674 lines
16 KiB
C
674 lines
16 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/*! \file liquidio_common.h
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* \brief Common: Structures and macros used in PCI-NIC package by core and
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* host driver.
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*/
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#ifndef __LIQUIDIO_COMMON_H__
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#define __LIQUIDIO_COMMON_H__
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#include "octeon_config.h"
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#define LIQUIDIO_VERSION "1.1.9"
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#define LIQUIDIO_MAJOR_VERSION 1
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#define LIQUIDIO_MINOR_VERSION 1
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#define LIQUIDIO_MICRO_VERSION 9
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#define CONTROL_IQ 0
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/** Tag types used by Octeon cores in its work. */
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enum octeon_tag_type {
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ORDERED_TAG = 0,
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ATOMIC_TAG = 1,
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NULL_TAG = 2,
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NULL_NULL_TAG = 3
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};
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/* pre-defined host->NIC tag values */
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#define LIO_CONTROL (0x11111110)
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#define LIO_DATA(i) (0x11111111 + (i))
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/* Opcodes used by host driver/apps to perform operations on the core.
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* These are used to identify the major subsystem that the operation
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* is for.
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*/
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#define OPCODE_CORE 0 /* used for generic core operations */
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#define OPCODE_NIC 1 /* used for NIC operations */
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#define OPCODE_LAST OPCODE_NIC
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/* Subcodes are used by host driver/apps to identify the sub-operation
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* for the core. They only need to by unique for a given subsystem.
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*/
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#define OPCODE_SUBCODE(op, sub) (((op & 0x0f) << 8) | ((sub) & 0x7f))
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/** OPCODE_CORE subcodes. For future use. */
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/** OPCODE_NIC subcodes */
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/* This subcode is sent by core PCI driver to indicate cores are ready. */
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#define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
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#define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
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#define OPCODE_NIC_CMD 0x03
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#define OPCODE_NIC_INFO 0x04
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#define OPCODE_NIC_PORT_STATS 0x05
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#define OPCODE_NIC_MDIO45 0x06
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#define OPCODE_NIC_TIMESTAMP 0x07
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#define OPCODE_NIC_INTRMOD_CFG 0x08
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#define OPCODE_NIC_IF_CFG 0x09
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#define CORE_DRV_TEST_SCATTER_OP 0xFFF5
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#define OPCODE_SLOW_PATH(rh) \
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(OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
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OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
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/* Application codes advertised by the core driver initialization packet. */
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#define CVM_DRV_APP_START 0x0
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#define CVM_DRV_NO_APP 0
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#define CVM_DRV_APP_COUNT 0x2
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#define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
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#define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
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#define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
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#define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
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/* Macro to increment index.
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* Index is incremented by count; if the sum exceeds
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* max, index is wrapped-around to the start.
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*/
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#define INCR_INDEX(index, count, max) \
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do { \
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if (((index) + (count)) >= (max)) \
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index = ((index) + (count)) - (max); \
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else \
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index += (count); \
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} while (0)
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#define INCR_INDEX_BY1(index, max) \
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do { \
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if ((++(index)) == (max)) \
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index = 0; \
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} while (0)
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#define DECR_INDEX(index, count, max) \
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do { \
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if ((count) > (index)) \
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index = ((max) - ((count - index))); \
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else \
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index -= count; \
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} while (0)
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#define OCT_BOARD_NAME 32
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#define OCT_SERIAL_LEN 64
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/* Structure used by core driver to send indication that the Octeon
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* application is ready.
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*/
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struct octeon_core_setup {
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u64 corefreq;
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char boardname[OCT_BOARD_NAME];
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char board_serial_number[OCT_SERIAL_LEN];
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u64 board_rev_major;
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u64 board_rev_minor;
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};
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/*--------------------------- SCATTER GATHER ENTRY -----------------------*/
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/* The Scatter-Gather List Entry. The scatter or gather component used with
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* a Octeon input instruction has this format.
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*/
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struct octeon_sg_entry {
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/** The first 64 bit gives the size of data in each dptr.*/
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union {
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u16 size[4];
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u64 size64;
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} u;
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/** The 4 dptr pointers for this entry. */
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u64 ptr[4];
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};
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#define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
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/* \brief Add size to gather list
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* @param sg_entry scatter/gather entry
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* @param size size to add
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* @param pos position to add it.
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*/
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static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
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u16 size,
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u32 pos)
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{
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#ifdef __BIG_ENDIAN_BITFIELD
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sg_entry->u.size[pos] = size;
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#else
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sg_entry->u.size[3 - pos] = size;
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#endif
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}
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/*------------------------- End Scatter/Gather ---------------------------*/
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#define OCTNET_FRM_PTP_HEADER_SIZE 8
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#define OCTNET_FRM_HEADER_SIZE 30 /* PTP timestamp + VLAN + Ethernet */
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#define OCTNET_MIN_FRM_SIZE (64 + OCTNET_FRM_PTP_HEADER_SIZE)
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#define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
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#define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
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/** NIC Commands are sent using this Octeon Input Queue */
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#define OCTNET_CMD_Q 0
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/* NIC Command types */
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#define OCTNET_CMD_CHANGE_MTU 0x1
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#define OCTNET_CMD_CHANGE_MACADDR 0x2
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#define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
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#define OCTNET_CMD_RX_CTL 0x4
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#define OCTNET_CMD_SET_MULTI_LIST 0x5
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#define OCTNET_CMD_CLEAR_STATS 0x6
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/* command for setting the speed, duplex & autoneg */
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#define OCTNET_CMD_SET_SETTINGS 0x7
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#define OCTNET_CMD_SET_FLOW_CTL 0x8
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#define OCTNET_CMD_MDIO_READ_WRITE 0x9
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#define OCTNET_CMD_GPIO_ACCESS 0xA
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#define OCTNET_CMD_LRO_ENABLE 0xB
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#define OCTNET_CMD_LRO_DISABLE 0xC
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#define OCTNET_CMD_SET_RSS 0xD
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#define OCTNET_CMD_WRITE_SA 0xE
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#define OCTNET_CMD_DELETE_SA 0xF
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#define OCTNET_CMD_UPDATE_SA 0x12
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#define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
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#define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
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#define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
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#define OCTNET_CMD_VERBOSE_ENABLE 0x14
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#define OCTNET_CMD_VERBOSE_DISABLE 0x15
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/* RX(packets coming from wire) Checksum verification flags */
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/* TCP/UDP csum */
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#define CNNIC_L4SUM_VERIFIED 0x1
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#define CNNIC_IPSUM_VERIFIED 0x2
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#define CNNIC_TUN_CSUM_VERIFIED 0x4
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#define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
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/*LROIPV4 and LROIPV6 Flags*/
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#define OCTNIC_LROIPV4 0x1
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#define OCTNIC_LROIPV6 0x2
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/* Interface flags communicated between host driver and core app. */
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enum octnet_ifflags {
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OCTNET_IFFLAG_PROMISC = 0x01,
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OCTNET_IFFLAG_ALLMULTI = 0x02,
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OCTNET_IFFLAG_MULTICAST = 0x04,
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OCTNET_IFFLAG_BROADCAST = 0x08,
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OCTNET_IFFLAG_UNICAST = 0x10
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};
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/* wqe
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* --------------- 0
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* | wqe word0-3 |
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* --------------- 32
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* | PCI IH |
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* --------------- 40
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* | RPTR |
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* --------------- 48
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* | PCI IRH |
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* --------------- 56
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* | OCT_NET_CMD |
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* --------------- 64
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* | Addtl 8-BData |
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* | |
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* ---------------
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*/
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union octnet_cmd {
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u64 u64;
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struct {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 cmd:5;
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u64 more:6; /* How many udd words follow the command */
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u64 param1:29;
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u64 param2:16;
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u64 param3:8;
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#else
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u64 param3:8;
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u64 param2:16;
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u64 param1:29;
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u64 more:6;
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u64 cmd:5;
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#endif
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} s;
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};
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#define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
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/** Instruction Header */
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struct octeon_instr_ih {
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#ifdef __BIG_ENDIAN_BITFIELD
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/** Raw mode indicator 1 = RAW */
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u64 raw:1;
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/** Gather indicator 1=gather*/
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u64 gather:1;
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/** Data length OR no. of entries in gather list */
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u64 dlengsz:14;
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/** Front Data size */
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u64 fsz:6;
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/** Packet Order / Work Unit selection (1 of 8)*/
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u64 qos:3;
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/** Core group selection (1 of 16) */
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u64 grp:4;
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/** Short Raw Packet Indicator 1=short raw pkt */
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u64 rs:1;
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/** Tag type */
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u64 tagtype:2;
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/** Tag Value */
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u64 tag:32;
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#else
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/** Tag Value */
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u64 tag:32;
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/** Tag type */
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u64 tagtype:2;
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/** Short Raw Packet Indicator 1=short raw pkt */
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u64 rs:1;
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/** Core group selection (1 of 16) */
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u64 grp:4;
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/** Packet Order / Work Unit selection (1 of 8)*/
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u64 qos:3;
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/** Front Data size */
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u64 fsz:6;
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/** Data length OR no. of entries in gather list */
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u64 dlengsz:14;
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/** Gather indicator 1=gather*/
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u64 gather:1;
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/** Raw mode indicator 1 = RAW */
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u64 raw:1;
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#endif
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};
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/** Input Request Header */
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struct octeon_instr_irh {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 opcode:4;
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u64 rflag:1;
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u64 subcode:7;
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u64 len:3;
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u64 rid:13;
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u64 reserved:4;
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u64 ossp:32; /* opcode/subcode specific parameters */
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#else
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u64 ossp:32; /* opcode/subcode specific parameters */
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u64 reserved:4;
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u64 rid:13;
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u64 len:3;
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u64 subcode:7;
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u64 rflag:1;
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u64 opcode:4;
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#endif
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};
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/** Return Data Parameters */
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struct octeon_instr_rdp {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 reserved:49;
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u64 pcie_port:3;
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u64 rlen:12;
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#else
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u64 rlen:12;
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u64 pcie_port:3;
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u64 reserved:49;
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#endif
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};
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/** Receive Header */
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union octeon_rh {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 u64;
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struct {
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u64 opcode:4;
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u64 subcode:8;
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u64 len:3; /** additional 64-bit words */
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u64 rid:13; /** request id in response to pkt sent by host */
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u64 reserved:4;
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u64 ossp:32; /** opcode/subcode specific parameters */
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} r;
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struct {
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u64 opcode:4;
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u64 subcode:8;
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u64 len:3; /** additional 64-bit words */
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u64 rid:13; /** request id in response to pkt sent by host */
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u64 extra:24;
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u64 link:8;
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u64 csum_verified:3; /** checksum verified. */
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u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
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} r_dh;
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struct {
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u64 opcode:4;
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u64 subcode:8;
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u64 len:3; /** additional 64-bit words */
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u64 rid:13; /** request id in response to pkt sent by host */
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u64 num_gmx_ports:8;
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u64 max_nic_ports:8;
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u64 app_cap_flags:4;
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u64 app_mode:16;
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} r_core_drv_init;
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struct {
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u64 opcode:4;
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u64 subcode:8;
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u64 len:3; /** additional 64-bit words */
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u64 rid:13;
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u64 reserved:4;
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u64 extra:25;
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u64 ifidx:7;
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} r_nic_info;
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#else
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u64 u64;
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struct {
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u64 ossp:32; /** opcode/subcode specific parameters */
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u64 reserved:4;
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u64 rid:13; /** req id in response to pkt sent by host */
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u64 len:3; /** additional 64-bit words */
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u64 subcode:8;
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u64 opcode:4;
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} r;
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struct {
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u64 has_hwtstamp:1; /** 1 = has hwtstamp */
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u64 csum_verified:3; /** checksum verified. */
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u64 link:8;
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u64 extra:24;
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u64 rid:13; /** req id in response to pkt sent by host */
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u64 len:3; /** additional 64-bit words */
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u64 subcode:8;
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u64 opcode:4;
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} r_dh;
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struct {
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u64 app_mode:16;
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u64 app_cap_flags:4;
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u64 max_nic_ports:8;
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u64 num_gmx_ports:8;
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u64 rid:13;
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u64 len:3; /** additional 64-bit words */
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u64 subcode:8;
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u64 opcode:4;
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} r_core_drv_init;
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struct {
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u64 ifidx:7;
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u64 extra:25;
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u64 reserved:4;
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u64 rid:13;
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u64 len:3; /** additional 64-bit words */
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u64 subcode:8;
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u64 opcode:4;
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} r_nic_info;
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#endif
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};
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#define OCT_RH_SIZE (sizeof(union octeon_rh))
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#define OCT_PKT_PARAM_IPV4OPTS 1
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#define OCT_PKT_PARAM_IPV6EXTHDR 2
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union octnic_packet_params {
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u32 u32;
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struct {
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#ifdef __BIG_ENDIAN_BITFIELD
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u32 reserved:6;
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u32 tnl_csum:1;
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u32 ip_csum:1;
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u32 ipv4opts_ipv6exthdr:2;
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u32 ipsec_ops:4;
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u32 tsflag:1;
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u32 csoffset:9;
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u32 ifidx:8;
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#else
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u32 ifidx:8;
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u32 csoffset:9;
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u32 tsflag:1;
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u32 ipsec_ops:4;
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u32 ipv4opts_ipv6exthdr:2;
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u32 ip_csum:1;
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u32 tnl_csum:1;
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u32 reserved:6;
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#endif
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} s;
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};
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/** Status of a RGMII Link on Octeon as seen by core driver. */
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union oct_link_status {
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u64 u64;
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struct {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 duplex:8;
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u64 status:8;
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u64 mtu:16;
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u64 speed:16;
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u64 autoneg:1;
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u64 interface:4;
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u64 pause:1;
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u64 reserved:10;
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#else
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u64 reserved:10;
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u64 pause:1;
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u64 interface:4;
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u64 autoneg:1;
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u64 speed:16;
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u64 mtu:16;
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u64 status:8;
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u64 duplex:8;
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#endif
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} s;
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};
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/** Information for a OCTEON ethernet interface shared between core & host. */
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struct oct_link_info {
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union oct_link_status link;
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u64 hw_addr;
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#ifdef __BIG_ENDIAN_BITFIELD
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u16 gmxport;
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u8 rsvd[3];
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u8 num_txpciq;
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u8 num_rxpciq;
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u8 ifidx;
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#else
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u8 ifidx;
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u8 num_rxpciq;
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u8 num_txpciq;
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u8 rsvd[3];
|
|
u16 gmxport;
|
|
#endif
|
|
|
|
u8 txpciq[MAX_IOQS_PER_NICIF];
|
|
u8 rxpciq[MAX_IOQS_PER_NICIF];
|
|
};
|
|
|
|
#define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
|
|
|
|
struct liquidio_if_cfg_info {
|
|
u64 ifidx;
|
|
u64 iqmask; /** mask for IQs enabled for the port */
|
|
u64 oqmask; /** mask for OQs enabled for the port */
|
|
struct oct_link_info linfo; /** initial link information */
|
|
};
|
|
|
|
/** Stats for each NIC port in RX direction. */
|
|
struct nic_rx_stats {
|
|
/* link-level stats */
|
|
u64 total_rcvd;
|
|
u64 bytes_rcvd;
|
|
u64 total_bcst;
|
|
u64 total_mcst;
|
|
u64 runts;
|
|
u64 ctl_rcvd;
|
|
u64 fifo_err; /* Accounts for over/under-run of buffers */
|
|
u64 dmac_drop;
|
|
u64 fcs_err;
|
|
u64 jabber_err;
|
|
u64 l2_err;
|
|
u64 frame_err;
|
|
|
|
/* firmware stats */
|
|
u64 fw_total_rcvd;
|
|
u64 fw_total_fwd;
|
|
u64 fw_err_pko;
|
|
u64 fw_err_link;
|
|
u64 fw_err_drop;
|
|
u64 fw_lro_pkts; /* Number of packets that are LROed */
|
|
u64 fw_lro_octs; /* Number of octets that are LROed */
|
|
u64 fw_total_lro; /* Number of LRO packets formed */
|
|
u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
|
|
/* intrmod: packet forward rate */
|
|
u64 fwd_rate;
|
|
};
|
|
|
|
/** Stats for each NIC port in RX direction. */
|
|
struct nic_tx_stats {
|
|
/* link-level stats */
|
|
u64 total_pkts_sent;
|
|
u64 total_bytes_sent;
|
|
u64 mcast_pkts_sent;
|
|
u64 bcast_pkts_sent;
|
|
u64 ctl_sent;
|
|
u64 one_collision_sent; /* Packets sent after one collision*/
|
|
u64 multi_collision_sent; /* Packets sent after multiple collision*/
|
|
u64 max_collision_fail; /* Packets not sent due to max collisions */
|
|
u64 max_deferral_fail; /* Packets not sent due to max deferrals */
|
|
u64 fifo_err; /* Accounts for over/under-run of buffers */
|
|
u64 runts;
|
|
u64 total_collisions; /* Total number of collisions detected */
|
|
|
|
/* firmware stats */
|
|
u64 fw_total_sent;
|
|
u64 fw_total_fwd;
|
|
u64 fw_err_pko;
|
|
u64 fw_err_link;
|
|
u64 fw_err_drop;
|
|
};
|
|
|
|
struct oct_link_stats {
|
|
struct nic_rx_stats fromwire;
|
|
struct nic_tx_stats fromhost;
|
|
|
|
};
|
|
|
|
#define LIO68XX_LED_CTRL_ADDR 0x3501
|
|
#define LIO68XX_LED_CTRL_CFGON 0x1f
|
|
#define LIO68XX_LED_CTRL_CFGOFF 0x100
|
|
#define LIO68XX_LED_BEACON_ADDR 0x3508
|
|
#define LIO68XX_LED_BEACON_CFGON 0x47fd
|
|
#define LIO68XX_LED_BEACON_CFGOFF 0x11fc
|
|
#define VITESSE_PHY_GPIO_DRIVEON 0x1
|
|
#define VITESSE_PHY_GPIO_CFG 0x8
|
|
#define VITESSE_PHY_GPIO_DRIVEOFF 0x4
|
|
#define VITESSE_PHY_GPIO_HIGH 0x2
|
|
#define VITESSE_PHY_GPIO_LOW 0x3
|
|
|
|
struct oct_mdio_cmd {
|
|
u64 op;
|
|
u64 mdio_addr;
|
|
u64 value1;
|
|
u64 value2;
|
|
u64 value3;
|
|
};
|
|
|
|
#define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
|
|
|
|
#define LIO_INTRMOD_CHECK_INTERVAL 1
|
|
#define LIO_INTRMOD_MAXPKT_RATETHR 196608 /* max pkt rate threshold */
|
|
#define LIO_INTRMOD_MINPKT_RATETHR 9216 /* min pkt rate threshold */
|
|
#define LIO_INTRMOD_MAXCNT_TRIGGER 384 /* max pkts to trigger interrupt */
|
|
#define LIO_INTRMOD_MINCNT_TRIGGER 1 /* min pkts to trigger interrupt */
|
|
#define LIO_INTRMOD_MAXTMR_TRIGGER 128 /* max time to trigger interrupt */
|
|
#define LIO_INTRMOD_MINTMR_TRIGGER 32 /* min time to trigger interrupt */
|
|
|
|
struct oct_intrmod_cfg {
|
|
u64 intrmod_enable;
|
|
u64 intrmod_check_intrvl;
|
|
u64 intrmod_maxpkt_ratethr;
|
|
u64 intrmod_minpkt_ratethr;
|
|
u64 intrmod_maxcnt_trigger;
|
|
u64 intrmod_maxtmr_trigger;
|
|
u64 intrmod_mincnt_trigger;
|
|
u64 intrmod_mintmr_trigger;
|
|
};
|
|
|
|
#define BASE_QUEUE_NOT_REQUESTED 65535
|
|
|
|
union oct_nic_if_cfg {
|
|
u64 u64;
|
|
struct {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
u64 base_queue:16;
|
|
u64 num_iqueues:16;
|
|
u64 num_oqueues:16;
|
|
u64 gmx_port_id:8;
|
|
u64 reserved:8;
|
|
#else
|
|
u64 reserved:8;
|
|
u64 gmx_port_id:8;
|
|
u64 num_oqueues:16;
|
|
u64 num_iqueues:16;
|
|
u64 base_queue:16;
|
|
#endif
|
|
} s;
|
|
};
|
|
|
|
#endif
|