336 lines
10 KiB
C
336 lines
10 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include <linux/string.h>
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#include <linux/bitops.h>
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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/**
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* DOC: buffer object tiling
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*
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* i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
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* declare fence register requirements.
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*
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* In principle GEM doesn't care at all about the internal data layout of an
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* object, and hence it also doesn't care about tiling or swizzling. There's two
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* exceptions:
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*
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* - For X and Y tiling the hardware provides detilers for CPU access, so called
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* fences. Since there's only a limited amount of them the kernel must manage
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* these, and therefore userspace must tell the kernel the object tiling if it
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* wants to use fences for detiling.
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* - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
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* depends upon the physical page frame number. When swapping such objects the
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* page frame number might change and the kernel must be able to fix this up
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* and hence now the tiling. Note that on a subset of platforms with
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* asymmetric memory channel population the swizzling pattern changes in an
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* unknown way, and for those the kernel simply forbids swapping completely.
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*
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* Since neither of this applies for new tiling layouts on modern platforms like
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* W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
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* Anything else can be handled in userspace entirely without the kernel's
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* invovlement.
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*/
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/* Check pitch constriants for all chips & tiling formats */
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static bool
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i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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{
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int tile_width;
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/* Linear is always fine */
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if (tiling_mode == I915_TILING_NONE)
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return true;
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if (IS_GEN2(dev) ||
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(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
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tile_width = 128;
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else
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tile_width = 512;
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/* check maximum stride & object size */
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/* i965+ stores the end address of the gtt mapping in the fence
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* reg, so dont bother to check the size */
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if (INTEL_INFO(dev)->gen >= 7) {
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if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
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return false;
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} else if (INTEL_INFO(dev)->gen >= 4) {
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if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
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return false;
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} else {
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if (stride > 8192)
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return false;
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if (IS_GEN3(dev)) {
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if (size > I830_FENCE_MAX_SIZE_VAL << 20)
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return false;
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} else {
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if (size > I830_FENCE_MAX_SIZE_VAL << 19)
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return false;
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}
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}
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if (stride < tile_width)
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return false;
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/* 965+ just needs multiples of tile width */
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if (INTEL_INFO(dev)->gen >= 4) {
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if (stride & (tile_width - 1))
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return false;
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return true;
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}
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/* Pre-965 needs power of two tile widths */
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if (stride & (stride - 1))
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return false;
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return true;
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}
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/* Is the current GTT allocation valid for the change in tiling? */
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static bool
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i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
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{
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u32 size;
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if (tiling_mode == I915_TILING_NONE)
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return true;
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if (INTEL_INFO(obj->base.dev)->gen >= 4)
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return true;
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if (IS_GEN3(obj->base.dev)) {
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if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
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return false;
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} else {
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if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
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return false;
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}
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size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
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if (i915_gem_obj_ggtt_size(obj) != size)
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return false;
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if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
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return false;
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return true;
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}
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/**
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* i915_gem_set_tiling - IOCTL handler to set tiling mode
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* @dev: DRM device
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* @data: data pointer for the ioctl
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* @file: DRM file for the ioctl call
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*
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* Sets the tiling mode of an object, returning the required swizzling of
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* bit 6 of addresses in the object.
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*
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* Called by the user via ioctl.
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*
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* Returns:
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* Zero on success, negative errno on failure.
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*/
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int
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i915_gem_set_tiling(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_gem_set_tiling *args = data;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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int ret = 0;
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obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
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if (&obj->base == NULL)
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return -ENOENT;
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if (!i915_tiling_ok(dev,
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args->stride, obj->base.size, args->tiling_mode)) {
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drm_gem_object_unreference_unlocked(&obj->base);
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return -EINVAL;
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}
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev->struct_mutex);
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if (obj->pin_display || obj->framebuffer_references) {
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ret = -EBUSY;
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goto err;
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}
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if (args->tiling_mode == I915_TILING_NONE) {
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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args->stride = 0;
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} else {
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if (args->tiling_mode == I915_TILING_X)
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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else
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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/* Hide bit 17 swizzling from the user. This prevents old Mesa
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* from aborting the application on sw fallbacks to bit 17,
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* and we use the pread/pwrite bit17 paths to swizzle for it.
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* If there was a user that was relying on the swizzle
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* information for drm_intel_bo_map()ed reads/writes this would
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* break it, but we don't have any of those.
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*/
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
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/* If we can't handle the swizzling, make it untiled. */
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
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args->tiling_mode = I915_TILING_NONE;
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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args->stride = 0;
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}
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}
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if (args->tiling_mode != obj->tiling_mode ||
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args->stride != obj->stride) {
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/* We need to rebind the object if its current allocation
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* no longer meets the alignment restrictions for its new
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* tiling mode. Otherwise we can just leave it alone, but
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* need to ensure that any fence register is updated before
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* the next fenced (either through the GTT or by the BLT unit
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* on older GPUs) access.
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*
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* After updating the tiling parameters, we then flag whether
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* we need to update an associated fence register. Note this
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* has to also include the unfenced register the GPU uses
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* whilst executing a fenced command for an untiled object.
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*/
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if (obj->map_and_fenceable &&
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!i915_gem_object_fence_ok(obj, args->tiling_mode))
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ret = i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
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if (ret == 0) {
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if (obj->pages &&
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obj->madv == I915_MADV_WILLNEED &&
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dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
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if (args->tiling_mode == I915_TILING_NONE)
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i915_gem_object_unpin_pages(obj);
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if (obj->tiling_mode == I915_TILING_NONE)
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i915_gem_object_pin_pages(obj);
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}
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obj->fence_dirty =
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obj->last_fenced_req ||
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obj->fence_reg != I915_FENCE_REG_NONE;
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obj->tiling_mode = args->tiling_mode;
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obj->stride = args->stride;
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/* Force the fence to be reacquired for GTT access */
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i915_gem_release_mmap(obj);
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}
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}
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/* we have to maintain this existing ABI... */
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args->stride = obj->stride;
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args->tiling_mode = obj->tiling_mode;
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/* Try to preallocate memory required to save swizzling on put-pages */
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if (i915_gem_object_needs_bit17_swizzle(obj)) {
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if (obj->bit_17 == NULL) {
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obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
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sizeof(long), GFP_KERNEL);
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}
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} else {
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kfree(obj->bit_17);
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obj->bit_17 = NULL;
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}
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err:
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drm_gem_object_unreference(&obj->base);
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mutex_unlock(&dev->struct_mutex);
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intel_runtime_pm_put(dev_priv);
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return ret;
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}
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/**
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* i915_gem_get_tiling - IOCTL handler to get tiling mode
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* @dev: DRM device
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* @data: data pointer for the ioctl
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* @file: DRM file for the ioctl call
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*
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* Returns the current tiling mode and required bit 6 swizzling for the object.
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*
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* Called by the user via ioctl.
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*
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* Returns:
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* Zero on success, negative errno on failure.
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*/
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int
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i915_gem_get_tiling(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_gem_get_tiling *args = data;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
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if (&obj->base == NULL)
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return -ENOENT;
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mutex_lock(&dev->struct_mutex);
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args->tiling_mode = obj->tiling_mode;
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switch (obj->tiling_mode) {
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case I915_TILING_X:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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break;
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case I915_TILING_Y:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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break;
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case I915_TILING_NONE:
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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break;
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default:
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DRM_ERROR("unknown tiling mode\n");
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}
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/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
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if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
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args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
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else
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args->phys_swizzle_mode = args->swizzle_mode;
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
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drm_gem_object_unreference(&obj->base);
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mutex_unlock(&dev->struct_mutex);
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return 0;
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}
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