330 lines
8.6 KiB
C
330 lines
8.6 KiB
C
/*
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* Platform support for LPC32xx SoC
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/eeprom.h>
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#include <linux/gpio.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/amba/pl022.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/amba/pl08x.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <mach/board.h>
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#include <mach/gpio-lpc32xx.h>
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#include "common.h"
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/*
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* Mapped GPIOLIB GPIOs
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*/
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#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
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#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
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#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
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/*
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* AMBA LCD controller
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*/
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static struct clcd_panel conn_lcd_panel = {
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.mode = {
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.name = "QVGA portrait",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 191828,
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.left_margin = 22,
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.right_margin = 11,
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.upper_margin = 2,
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.lower_margin = 1,
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.hsync_len = 5,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = (TIM2_IVS | TIM2_IHS),
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.cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
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CNTL_LCDBPP16_565),
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.bpp = 16,
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};
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#define PANEL_SIZE (3 * SZ_64K)
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static int lpc32xx_clcd_setup(struct clcd_fb *fb)
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{
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dma_addr_t dma;
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fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
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PANEL_SIZE, &dma, GFP_KERNEL);
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if (!fb->fb.screen_base) {
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printk(KERN_ERR "CLCD: unable to map framebuffer\n");
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return -ENOMEM;
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}
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fb->fb.fix.smem_start = dma;
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fb->fb.fix.smem_len = PANEL_SIZE;
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fb->panel = &conn_lcd_panel;
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if (gpio_request(LCD_POWER_GPIO, "LCD power"))
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printk(KERN_ERR "Error requesting gpio %u",
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LCD_POWER_GPIO);
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else if (gpio_direction_output(LCD_POWER_GPIO, 1))
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printk(KERN_ERR "Error setting gpio %u to output",
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LCD_POWER_GPIO);
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if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
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printk(KERN_ERR "Error requesting gpio %u",
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BKL_POWER_GPIO);
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else if (gpio_direction_output(BKL_POWER_GPIO, 1))
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printk(KERN_ERR "Error setting gpio %u to output",
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BKL_POWER_GPIO);
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return 0;
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}
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static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
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{
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return dma_mmap_writecombine(&fb->dev->dev, vma,
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fb->fb.screen_base, fb->fb.fix.smem_start,
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fb->fb.fix.smem_len);
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}
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static void lpc32xx_clcd_remove(struct clcd_fb *fb)
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{
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dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
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fb->fb.screen_base, fb->fb.fix.smem_start);
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}
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/*
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* On some early LCD modules (1307.0), the backlight logic is inverted.
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* For those board variants, swap the disable and enable states for
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* BKL_POWER_GPIO.
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*/
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static void clcd_disable(struct clcd_fb *fb)
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{
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gpio_set_value(BKL_POWER_GPIO, 0);
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gpio_set_value(LCD_POWER_GPIO, 0);
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}
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static void clcd_enable(struct clcd_fb *fb)
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{
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gpio_set_value(BKL_POWER_GPIO, 1);
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gpio_set_value(LCD_POWER_GPIO, 1);
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}
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static struct clcd_board lpc32xx_clcd_data = {
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.name = "Phytec LCD",
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.disable = clcd_disable,
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.enable = clcd_enable,
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.setup = lpc32xx_clcd_setup,
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.mmap = lpc32xx_clcd_mmap,
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.remove = lpc32xx_clcd_remove,
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};
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/*
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* AMBA SSP (SPI)
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*/
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static void phy3250_spi_cs_set(u32 control)
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{
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gpio_set_value(SPI0_CS_GPIO, (int) control);
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}
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static struct pl022_config_chip spi0_chip_info = {
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.com_mode = INTERRUPT_TRANSFER,
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.iface = SSP_INTERFACE_MOTOROLA_SPI,
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.hierarchy = SSP_MASTER,
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.slave_tx_disable = 0,
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.rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
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.tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
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.ctrl_len = SSP_BITS_8,
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.wait_state = SSP_MWIRE_WAIT_ZERO,
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.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
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.cs_control = phy3250_spi_cs_set,
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};
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static struct pl022_ssp_controller lpc32xx_ssp0_data = {
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.bus_id = 0,
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.num_chipselect = 1,
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.enable_dma = 0,
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};
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static struct pl022_ssp_controller lpc32xx_ssp1_data = {
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.bus_id = 1,
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.num_chipselect = 1,
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.enable_dma = 0,
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};
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/* AT25 driver registration */
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static int __init phy3250_spi_board_register(void)
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{
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct spi_board_info info[] = {
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{
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.modalias = "spidev",
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.max_speed_hz = 5000000,
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.bus_num = 0,
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.chip_select = 0,
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.controller_data = &spi0_chip_info,
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},
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};
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#else
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static struct spi_eeprom eeprom = {
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.name = "at25256a",
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.byte_len = 0x8000,
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.page_size = 64,
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.flags = EE_ADDR2,
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};
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static struct spi_board_info info[] = {
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{
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.modalias = "at25",
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.max_speed_hz = 5000000,
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.bus_num = 0,
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.chip_select = 0,
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.mode = SPI_MODE_0,
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.platform_data = &eeprom,
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.controller_data = &spi0_chip_info,
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},
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};
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#endif
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return spi_register_board_info(info, ARRAY_SIZE(info));
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}
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arch_initcall(phy3250_spi_board_register);
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static struct pl08x_platform_data pl08x_pd = {
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};
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static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
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OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
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OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
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OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
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OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
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{ }
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};
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static void __init lpc3250_machine_init(void)
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{
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u32 tmp;
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/* Setup SLC NAND controller muxing */
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__raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
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LPC32XX_CLKPWR_NAND_CLK_CTRL);
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/* Setup LCD muxing to RGB565 */
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tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
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~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
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LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
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tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
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__raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
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/* Set up USB power */
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tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
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tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
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LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
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__raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
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/* Set up I2C pull levels */
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tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
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tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
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LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
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__raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
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/* Disable IrDA pulsing support on UART6 */
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tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
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tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
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__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
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/* Enable DMA for I2S1 channel */
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tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
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tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
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__raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
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lpc32xx_serial_init();
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/*
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* AMBA peripheral clocks need to be enabled prior to AMBA device
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* detection or a data fault will occur, so enable the clocks
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* here.
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*/
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tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
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__raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
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LPC32XX_CLKPWR_LCDCLK_CTRL);
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tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
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__raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
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LPC32XX_CLKPWR_SSP_CLK_CTRL);
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tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
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__raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
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LPC32XX_CLKPWR_DMA_CLK_CTRL);
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/* Test clock needed for UDA1380 initial init */
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__raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
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LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
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LPC32XX_CLKPWR_TEST_CLK_SEL);
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of_platform_populate(NULL, of_default_bus_match_table,
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lpc32xx_auxdata_lookup, NULL);
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/* Register GPIOs used on this board */
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if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
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printk(KERN_ERR "Error requesting gpio %u",
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SPI0_CS_GPIO);
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else if (gpio_direction_output(SPI0_CS_GPIO, 1))
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printk(KERN_ERR "Error setting gpio %u to output",
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SPI0_CS_GPIO);
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}
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static char const *lpc32xx_dt_compat[] __initdata = {
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"nxp,lpc3220",
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"nxp,lpc3230",
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"nxp,lpc3240",
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"nxp,lpc3250",
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NULL
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};
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DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
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.atag_offset = 0x100,
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.map_io = lpc32xx_map_io,
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.init_irq = lpc32xx_init_irq,
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.timer = &lpc32xx_timer,
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.init_machine = lpc3250_machine_init,
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.dt_compat = lpc32xx_dt_compat,
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.restart = lpc23xx_restart,
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MACHINE_END
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