441 lines
16 KiB
C
441 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Driver for ITE Tech Inc. IT8712F/IT8512F CIR
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*
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* Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
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*/
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/* platform driver name to register */
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#define ITE_DRIVER_NAME "ite-cir"
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/* FIFO sizes */
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#define ITE_TX_FIFO_LEN 32
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#define ITE_RX_FIFO_LEN 32
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/* interrupt types */
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#define ITE_IRQ_TX_FIFO 1
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#define ITE_IRQ_RX_FIFO 2
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#define ITE_IRQ_RX_FIFO_OVERRUN 4
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/* forward declaration */
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struct ite_dev;
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/* struct for storing the parameters of different recognized devices */
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struct ite_dev_params {
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/* model of the device */
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const char *model;
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/* size of the I/O region */
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int io_region_size;
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/* IR pnp I/O resource number */
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int io_rsrc_no;
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/* hw-specific operation function pointers; most of these must be
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* called while holding the spin lock, except for the TX FIFO length
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* one */
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/* get pending interrupt causes */
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int (*get_irq_causes) (struct ite_dev *dev);
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/* enable rx */
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void (*enable_rx) (struct ite_dev *dev);
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/* make rx enter the idle state; keep listening for a pulse, but stop
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* streaming space bytes */
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void (*idle_rx) (struct ite_dev *dev);
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/* disable rx completely */
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void (*disable_rx) (struct ite_dev *dev);
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/* read bytes from RX FIFO; return read count */
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int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size);
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/* enable tx FIFO space available interrupt */
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void (*enable_tx_interrupt) (struct ite_dev *dev);
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/* disable tx FIFO space available interrupt */
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void (*disable_tx_interrupt) (struct ite_dev *dev);
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/* get number of full TX FIFO slots */
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int (*get_tx_used_slots) (struct ite_dev *dev);
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/* put a byte to the TX FIFO */
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void (*put_tx_byte) (struct ite_dev *dev, u8 value);
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/* disable hardware completely */
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void (*disable) (struct ite_dev *dev);
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/* initialize the hardware */
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void (*init_hardware) (struct ite_dev *dev);
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/* set the carrier parameters */
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void (*set_carrier_params) (struct ite_dev *dev, bool high_freq,
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bool use_demodulator, u8 carrier_freq_bits,
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u8 allowance_bits, u8 pulse_width_bits);
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};
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/* ITE CIR device structure */
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struct ite_dev {
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struct pnp_dev *pdev;
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struct rc_dev *rdev;
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/* sync data */
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spinlock_t lock;
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bool transmitting;
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/* transmit support */
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wait_queue_head_t tx_queue, tx_ended;
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/* rx low carrier frequency, in Hz, 0 means no demodulation */
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unsigned int rx_low_carrier_freq;
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/* tx high carrier frequency, in Hz, 0 means no demodulation */
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unsigned int rx_high_carrier_freq;
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/* tx carrier frequency, in Hz */
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unsigned int tx_carrier_freq;
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/* duty cycle, 0-100 */
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int tx_duty_cycle;
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/* hardware I/O settings */
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unsigned long cir_addr;
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int cir_irq;
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/* overridable copy of model parameters */
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const struct ite_dev_params *params;
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};
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/* common values for all kinds of hardware */
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/* baud rate divisor default */
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#define ITE_BAUDRATE_DIVISOR 1
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/* low-speed carrier frequency limits (Hz) */
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#define ITE_LCF_MIN_CARRIER_FREQ 27000
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#define ITE_LCF_MAX_CARRIER_FREQ 58000
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/* high-speed carrier frequency limits (Hz) */
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#define ITE_HCF_MIN_CARRIER_FREQ 400000
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#define ITE_HCF_MAX_CARRIER_FREQ 500000
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/* default carrier freq for when demodulator is off (Hz) */
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#define ITE_DEFAULT_CARRIER_FREQ 38000
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/* convert bits to us */
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#define ITE_BITS_TO_US(bits, sample_period) \
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((u32)((bits) * ITE_BAUDRATE_DIVISOR * (sample_period) / 1000))
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/*
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* n in RDCR produces a tolerance of +/- n * 6.25% around the center
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* carrier frequency...
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*
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* From two limit frequencies, L (low) and H (high), we can get both the
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* center frequency F = (L + H) / 2 and the variation from the center
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* frequency A = (H - L) / (H + L). We can use this in order to honor the
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* s_rx_carrier_range() call in ir-core. We'll suppose that any request
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* setting L=0 means we must shut down the demodulator.
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*/
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#define ITE_RXDCR_PER_10000_STEP 625
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/* high speed carrier freq values */
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#define ITE_CFQ_400 0x03
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#define ITE_CFQ_450 0x08
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#define ITE_CFQ_480 0x0b
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#define ITE_CFQ_500 0x0d
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/* values for pulse widths */
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#define ITE_TXMPW_A 0x02
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#define ITE_TXMPW_B 0x03
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#define ITE_TXMPW_C 0x04
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#define ITE_TXMPW_D 0x05
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#define ITE_TXMPW_E 0x06
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/* values for demodulator carrier range allowance */
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#define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */
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#define ITE_RXDCR_MAX 0x07 /* default carrier range */
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/* DR TX bits */
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#define ITE_TX_PULSE 0x00
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#define ITE_TX_SPACE 0x80
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#define ITE_TX_MAX_RLE 0x80
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#define ITE_TX_RLE_MASK 0x7f
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/*
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* IT8712F
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*
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* hardware data obtained from:
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*
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* IT8712F
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* Environment Control - Low Pin Count Input / Output
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* (EC - LPC I/O)
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* Preliminary Specification V0. 81
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*/
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/* register offsets */
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#define IT87_DR 0x00 /* data register */
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#define IT87_IER 0x01 /* interrupt enable register */
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#define IT87_RCR 0x02 /* receiver control register */
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#define IT87_TCR1 0x03 /* transmitter control register 1 */
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#define IT87_TCR2 0x04 /* transmitter control register 2 */
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#define IT87_TSR 0x05 /* transmitter status register */
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#define IT87_RSR 0x06 /* receiver status register */
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#define IT87_BDLR 0x05 /* baud rate divisor low byte register */
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#define IT87_BDHR 0x06 /* baud rate divisor high byte register */
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#define IT87_IIR 0x07 /* interrupt identification register */
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#define IT87_IOREG_LENGTH 0x08 /* length of register file */
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/* IER bits */
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#define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
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#define IT87_RDAIE 0x02 /* receiver data available interrupt enable */
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#define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */
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#define IT87_IEC 0x08 /* interrupt enable control */
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#define IT87_BR 0x10 /* baud rate register enable */
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#define IT87_RESET 0x20 /* reset */
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/* RCR bits */
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#define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */
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#define IT87_RXACT 0x08 /* receiver active */
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#define IT87_RXEND 0x10 /* receiver demodulation enable */
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#define IT87_RXEN 0x20 /* receiver enable */
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#define IT87_HCFS 0x40 /* high-speed carrier frequency select */
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#define IT87_RDWOS 0x80 /* receiver data without sync */
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/* TCR1 bits */
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#define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */
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#define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
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#define IT87_TXENDF 0x04 /* transmitter deferral */
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#define IT87_TXRLE 0x08 /* transmitter run length enable */
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#define IT87_FIFOTL 0x30 /* FIFO level threshold mask */
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#define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default
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* 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
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* 0x30 -> 25 */
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#define IT87_ILE 0x40 /* internal loopback enable */
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#define IT87_FIFOCLR 0x80 /* FIFO clear bit */
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/* TCR2 bits */
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#define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */
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#define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
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#define IT87_CFQ 0xf8 /* carrier frequency mask */
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#define IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */
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/* TSR bits */
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#define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */
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/* RSR bits */
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#define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */
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#define IT87_RXFTO 0x80 /* receiver FIFO time-out */
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/* IIR bits */
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#define IT87_IP 0x01 /* interrupt pending */
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#define IT87_II 0x06 /* interrupt identification mask */
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#define IT87_II_NOINT 0x00 /* no interrupt */
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#define IT87_II_TXLDL 0x02 /* transmitter low data level */
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#define IT87_II_RXDS 0x04 /* receiver data stored */
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#define IT87_II_RXFO 0x06 /* receiver FIFO overrun */
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/*
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* IT8512E/F
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*
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* Hardware data obtained from:
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*
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* IT8512E/F
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* Embedded Controller
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* Preliminary Specification V0.4.1
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*
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* Note that the CIR registers are not directly available to the host, because
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* they only are accessible to the integrated microcontroller. Thus, in order
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* use it, some kind of bridging is required. As the bridging may depend on
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* the controller firmware in use, we are going to use the PNP ID in order to
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* determine the strategy and ports available. See after these generic
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* IT8512E/F register definitions for register definitions for those
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* strategies.
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*/
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/* register offsets */
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#define IT85_C0DR 0x00 /* data register */
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#define IT85_C0MSTCR 0x01 /* master control register */
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#define IT85_C0IER 0x02 /* interrupt enable register */
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#define IT85_C0IIR 0x03 /* interrupt identification register */
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#define IT85_C0CFR 0x04 /* carrier frequency register */
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#define IT85_C0RCR 0x05 /* receiver control register */
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#define IT85_C0TCR 0x06 /* transmitter control register */
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#define IT85_C0SCK 0x07 /* slow clock control register */
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#define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
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#define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */
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#define IT85_C0TFSR 0x0a /* transmitter FIFO status register */
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#define IT85_C0RFSR 0x0b /* receiver FIFO status register */
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#define IT85_C0WCL 0x0d /* wakeup code length register */
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#define IT85_C0WCR 0x0e /* wakeup code read/write register */
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#define IT85_C0WPS 0x0f /* wakeup power control/status register */
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#define IT85_IOREG_LENGTH 0x10 /* length of register file */
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/* C0MSTCR bits */
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#define IT85_RESET 0x01 /* reset */
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#define IT85_FIFOCLR 0x02 /* FIFO clear bit */
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#define IT85_FIFOTL 0x0c /* FIFO level threshold mask */
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#define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default
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* 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
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* 0x0c -> 25 */
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#define IT85_ILE 0x10 /* internal loopback enable */
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#define IT85_ILSEL 0x20 /* internal loopback select */
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/* C0IER bits */
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#define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
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#define IT85_RDAIE 0x02 /* RX data available interrupt enable */
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#define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */
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#define IT85_IEC 0x80 /* interrupt enable function control */
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/* C0IIR bits */
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#define IT85_TLDLI 0x01 /* transmitter low data level interrupt */
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#define IT85_RDAI 0x02 /* receiver data available interrupt */
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#define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */
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#define IT85_NIP 0x80 /* no interrupt pending */
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/* C0CFR bits */
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#define IT85_CFQ 0x1f /* carrier frequency mask */
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#define IT85_HCFS 0x20 /* high speed carrier frequency select */
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/* C0RCR bits */
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#define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */
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#define IT85_RXACT 0x08 /* receiver active */
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#define IT85_RXEND 0x10 /* receiver demodulation enable */
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#define IT85_RDWOS 0x20 /* receiver data without sync */
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#define IT85_RXEN 0x80 /* receiver enable */
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/* C0TCR bits */
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#define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */
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#define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
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#define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */
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#define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
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#define IT85_TXENDF 0x20 /* transmitter deferral */
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#define IT85_TXRLE 0x40 /* transmitter run length enable */
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/* C0SCK bits */
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#define IT85_SCKS 0x01 /* slow clock select */
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#define IT85_TXDCKG 0x02 /* TXD clock gating */
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#define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */
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#define IT85_DLLTE 0x08 /* DLL test enable */
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#define IT85_BRCM 0x70 /* baud rate count mode */
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#define IT85_DLLOCK 0x80 /* DLL lock */
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/* C0TFSR bits */
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#define IT85_TXFBC 0x3f /* transmitter FIFO count mask */
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/* C0RFSR bits */
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#define IT85_RXFBC 0x3f /* receiver FIFO count mask */
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#define IT85_RXFTO 0x80 /* receiver FIFO time-out */
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/* C0WCL bits */
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#define IT85_WCL 0x3f /* wakeup code length mask */
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/* C0WPS bits */
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#define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */
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#define IT85_CIRPOIS 0x02 /* power on/off interrupt status */
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#define IT85_CIRPOII 0x04 /* power on/off interrupt identification */
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#define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */
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#define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */
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/*
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* ITE8708
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*
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* Hardware data obtained from hacked driver for IT8512 in this forum post:
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*
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* http://ubuntuforums.org/showthread.php?t=1028640
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*
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* Although there's no official documentation for that driver, analysis would
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* suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
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* selectable by a single bank-select bit that's mapped onto both banks. The
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* IT8512 registers are mapped in a different order, so that the first bank
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* maps the ones that are used more often, and two registers that share a
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* reserved high-order bit are placed at the same offset in both banks in
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* order to reuse the reserved bit as the bank select bit.
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*/
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/* register offsets */
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/* mapped onto both banks */
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#define IT8708_BANKSEL 0x07 /* bank select register */
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#define IT8708_HRAE 0x80 /* high registers access enable */
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/* mapped onto the low bank */
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#define IT8708_C0DR 0x00 /* data register */
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#define IT8708_C0MSTCR 0x01 /* master control register */
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#define IT8708_C0IER 0x02 /* interrupt enable register */
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#define IT8708_C0IIR 0x03 /* interrupt identification register */
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#define IT8708_C0RFSR 0x04 /* receiver FIFO status register */
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#define IT8708_C0RCR 0x05 /* receiver control register */
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#define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */
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#define IT8708_C0TCR 0x07 /* transmitter control register */
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/* mapped onto the high bank */
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#define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
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#define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */
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#define IT8708_C0CFR 0x04 /* carrier frequency register */
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/* registers whose bank mapping we don't know, since they weren't being used
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* in the hacked driver... most probably they belong to the high bank too,
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* since they fit in the holes the other registers leave */
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#define IT8708_C0SCK 0x03 /* slow clock control register */
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#define IT8708_C0WCL 0x05 /* wakeup code length register */
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#define IT8708_C0WCR 0x06 /* wakeup code read/write register */
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#define IT8708_C0WPS 0x07 /* wakeup power control/status register */
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#define IT8708_IOREG_LENGTH 0x08 /* length of register file */
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/* two more registers that are defined in the hacked driver, but can't be
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* found in the data sheets; no idea what they are or how they are accessed,
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* since the hacked driver doesn't seem to use them */
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#define IT8708_CSCRR 0x00
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#define IT8708_CGPINTR 0x01
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/* CSCRR bits */
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#define IT8708_CSCRR_SCRB 0x3f
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#define IT8708_CSCRR_PM 0x80
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/* CGPINTR bits */
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#define IT8708_CGPINT 0x01
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/*
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* ITE8709
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*
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* Hardware interfacing data obtained from the original lirc_ite8709 driver.
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* Verbatim from its sources:
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*
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* The ITE8709 device seems to be the combination of IT8512 superIO chip and
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* a specific firmware running on the IT8512's embedded micro-controller.
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* In addition of the embedded micro-controller, the IT8512 chip contains a
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* CIR module and several other modules. A few modules are directly accessible
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* by the host CPU, but most of them are only accessible by the
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* micro-controller. The CIR module is only accessible by the
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* micro-controller.
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*
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* The battery-backed SRAM module is accessible by the host CPU and the
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* micro-controller. So one of the MC's firmware role is to act as a bridge
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* between the host CPU and the CIR module. The firmware implements a kind of
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* communication protocol using the SRAM module as a shared memory. The IT8512
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* specification is publicly available on ITE's web site, but the
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* communication protocol is not, so it was reverse-engineered.
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*/
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/* register offsets */
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#define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */
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#define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */
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#define IT8709_IOREG_LENGTH 0x02 /* length of register file */
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/* register offsets inside the SRAM module */
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#define IT8709_MODE 0x1a /* request/ack byte */
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#define IT8709_REG_IDX 0x1b /* index of the CIR register to access */
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#define IT8709_REG_VAL 0x1c /* value read/to be written */
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#define IT8709_IIR 0x1e /* interrupt identification register */
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#define IT8709_RFSR 0x1f /* receiver FIFO status register */
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#define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */
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/* MODE values */
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#define IT8709_IDLE 0x00
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#define IT8709_WRITE 0x01
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#define IT8709_READ 0x02
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