166 lines
4.2 KiB
C
166 lines
4.2 KiB
C
/*
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* Xtensa MX interrupt distributor
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*
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* Copyright (C) 2002 - 2013 Tensilica, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <asm/mxregs.h>
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#define HW_IRQ_IPI_COUNT 2
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#define HW_IRQ_MX_BASE 2
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#define HW_IRQ_EXTERN_BASE 3
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static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
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static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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if (hw < HW_IRQ_IPI_COUNT) {
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struct irq_chip *irq_chip = d->host_data;
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irq_set_chip_and_handler_name(irq, irq_chip,
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handle_percpu_irq, "ipi");
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irq_set_status_flags(irq, IRQ_LEVEL);
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return 0;
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}
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
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return xtensa_irq_map(d, irq, hw);
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}
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/*
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* Device Tree IRQ specifier translation function which works with one or
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* two cell bindings. First cell value maps directly to the hwirq number.
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* Second cell if present specifies whether hwirq number is external (1) or
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* internal (0).
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*/
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static int xtensa_mx_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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return xtensa_irq_domain_xlate(intspec, intsize,
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intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE,
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out_hwirq, out_type);
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}
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static const struct irq_domain_ops xtensa_mx_irq_domain_ops = {
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.xlate = xtensa_mx_irq_domain_xlate,
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.map = xtensa_mx_irq_map,
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};
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void secondary_init_irq(void)
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{
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__this_cpu_write(cached_irq_mask,
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XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
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set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
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}
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static void xtensa_mx_irq_mask(struct irq_data *d)
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{
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unsigned int mask = 1u << d->hwirq;
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if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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HW_IRQ_MX_BASE), MIENG);
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} else {
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mask = __this_cpu_read(cached_irq_mask) & ~mask;
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__this_cpu_write(cached_irq_mask, mask);
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set_sr(mask, intenable);
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}
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}
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static void xtensa_mx_irq_unmask(struct irq_data *d)
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{
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unsigned int mask = 1u << d->hwirq;
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if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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HW_IRQ_MX_BASE), MIENGSET);
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} else {
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mask |= __this_cpu_read(cached_irq_mask);
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__this_cpu_write(cached_irq_mask, mask);
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set_sr(mask, intenable);
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}
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}
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static void xtensa_mx_irq_enable(struct irq_data *d)
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{
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xtensa_mx_irq_unmask(d);
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}
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static void xtensa_mx_irq_disable(struct irq_data *d)
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{
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xtensa_mx_irq_mask(d);
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}
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static void xtensa_mx_irq_ack(struct irq_data *d)
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{
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set_sr(1 << d->hwirq, intclear);
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}
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static int xtensa_mx_irq_retrigger(struct irq_data *d)
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{
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set_sr(1 << d->hwirq, intset);
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return 1;
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}
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static int xtensa_mx_irq_set_affinity(struct irq_data *d,
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const struct cpumask *dest, bool force)
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{
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int cpu = cpumask_any_and(dest, cpu_online_mask);
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unsigned mask = 1u << cpu;
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set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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return 0;
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}
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static struct irq_chip xtensa_mx_irq_chip = {
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.name = "xtensa-mx",
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.irq_enable = xtensa_mx_irq_enable,
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.irq_disable = xtensa_mx_irq_disable,
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.irq_mask = xtensa_mx_irq_mask,
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.irq_unmask = xtensa_mx_irq_unmask,
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.irq_ack = xtensa_mx_irq_ack,
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.irq_retrigger = xtensa_mx_irq_retrigger,
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.irq_set_affinity = xtensa_mx_irq_set_affinity,
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};
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int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
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{
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struct irq_domain *root_domain =
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irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
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&xtensa_mx_irq_domain_ops,
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&xtensa_mx_irq_chip);
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irq_set_default_host(root_domain);
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secondary_init_irq();
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return 0;
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}
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static int __init xtensa_mx_init(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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struct irq_domain *root_domain =
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irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
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&xtensa_mx_irq_chip);
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irq_set_default_host(root_domain);
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secondary_init_irq();
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return 0;
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}
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IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);
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