224 lines
5.9 KiB
C
224 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Low-Level PCI Access for i386 machines.
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*
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* (c) 1999 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/ioport.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
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#else
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#define DBG(fmt, ...) \
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do { \
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if (0) \
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printk(fmt, ##__VA_ARGS__); \
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} while (0)
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#endif
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#define PCI_PROBE_BIOS 0x0001
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#define PCI_PROBE_CONF1 0x0002
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#define PCI_PROBE_CONF2 0x0004
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#define PCI_PROBE_MMCONF 0x0008
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#define PCI_PROBE_MASK 0x000f
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#define PCI_PROBE_NOEARLY 0x0010
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#define PCI_NO_CHECKS 0x0400
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#define PCI_USE_PIRQ_MASK 0x0800
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#define PCI_ASSIGN_ROMS 0x1000
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#define PCI_BIOS_IRQ_SCAN 0x2000
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#define PCI_ASSIGN_ALL_BUSSES 0x4000
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#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
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#define PCI_USE__CRS 0x10000
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#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
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#define PCI_HAS_IO_ECS 0x40000
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#define PCI_NOASSIGN_ROMS 0x80000
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#define PCI_ROOT_NO_CRS 0x100000
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#define PCI_NOASSIGN_BARS 0x200000
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#define PCI_BIG_ROOT_WINDOW 0x400000
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extern unsigned int pci_probe;
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extern unsigned long pirq_table_addr;
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enum pci_bf_sort_state {
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pci_bf_sort_default,
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pci_force_nobf,
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pci_force_bf,
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pci_dmi_bf,
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};
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/* pci-i386.c */
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void pcibios_resource_survey(void);
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void pcibios_set_cache_line_size(void);
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/* pci-pc.c */
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extern int pcibios_last_bus;
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extern struct pci_ops pci_root_ops;
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void pcibios_scan_specific_bus(int busn);
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/* pci-irq.c */
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struct irq_info {
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u8 bus, devfn; /* Bus, device and function */
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struct {
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u8 link; /* IRQ line ID, chipset dependent,
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0 = not routed */
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u16 bitmap; /* Available IRQs */
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} __attribute__((packed)) irq[4];
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u8 slot; /* Slot number, 0=onboard */
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u8 rfu;
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} __attribute__((packed));
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struct irq_routing_table {
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u32 signature; /* PIRQ_SIGNATURE should be here */
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u16 version; /* PIRQ_VERSION */
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u16 size; /* Table size in bytes */
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u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
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u16 exclusive_irqs; /* IRQs devoted exclusively to
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PCI usage */
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u16 rtr_vendor, rtr_device; /* Vendor and device ID of
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interrupt router */
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u32 miniport_data; /* Crap */
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u8 rfu[11];
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u8 checksum; /* Modulo 256 checksum must give 0 */
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struct irq_info slots[0];
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} __attribute__((packed));
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extern unsigned int pcibios_irq_mask;
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extern raw_spinlock_t pci_config_lock;
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extern int (*pcibios_enable_irq)(struct pci_dev *dev);
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extern void (*pcibios_disable_irq)(struct pci_dev *dev);
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extern bool mp_should_keep_irq(struct device *dev);
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struct pci_raw_ops {
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int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *val);
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int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val);
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};
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extern const struct pci_raw_ops *raw_pci_ops;
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extern const struct pci_raw_ops *raw_pci_ext_ops;
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extern const struct pci_raw_ops pci_mmcfg;
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extern const struct pci_raw_ops pci_direct_conf1;
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extern bool port_cf9_safe;
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/* arch_initcall level */
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extern int pci_direct_probe(void);
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extern void pci_direct_init(int type);
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extern void pci_pcbios_init(void);
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extern void __init dmi_check_pciprobe(void);
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extern void __init dmi_check_skip_isa_align(void);
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/* some common used subsys_initcalls */
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#ifdef CONFIG_PCI
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extern int __init pci_acpi_init(void);
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#else
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static inline int __init pci_acpi_init(void)
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{
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return -EINVAL;
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}
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#endif
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extern void __init pcibios_irq_init(void);
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extern int __init pcibios_init(void);
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extern int pci_legacy_init(void);
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extern void pcibios_fixup_irqs(void);
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/* pci-mmconfig.c */
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/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
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#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
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struct pci_mmcfg_region {
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struct list_head list;
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struct resource res;
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u64 address;
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char __iomem *virt;
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u16 segment;
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u8 start_bus;
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u8 end_bus;
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char name[PCI_MMCFG_RESOURCE_NAME_LEN];
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};
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extern int __init pci_mmcfg_arch_init(void);
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extern void __init pci_mmcfg_arch_free(void);
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extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
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extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
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extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
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phys_addr_t addr);
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extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
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extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
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extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
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int end, u64 addr);
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extern struct list_head pci_mmcfg_list;
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#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
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/*
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* On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
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* %eax. No other source or target registers may be used. The following
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* mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's
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* Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
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* "MMIO Configuration Coding Requirements".
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*/
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static inline unsigned char mmio_config_readb(void __iomem *pos)
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{
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u8 val;
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asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned short mmio_config_readw(void __iomem *pos)
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{
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u16 val;
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asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned int mmio_config_readl(void __iomem *pos)
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{
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u32 val;
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asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline void mmio_config_writeb(void __iomem *pos, u8 val)
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{
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asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writew(void __iomem *pos, u16 val)
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{
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asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writel(void __iomem *pos, u32 val)
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{
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asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
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}
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#ifdef CONFIG_PCI
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# ifdef CONFIG_ACPI
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# define x86_default_pci_init pci_acpi_init
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# else
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# define x86_default_pci_init pci_legacy_init
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# endif
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# define x86_default_pci_init_irq pcibios_irq_init
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# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
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#else
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# define x86_default_pci_init NULL
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# define x86_default_pci_init_irq NULL
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# define x86_default_pci_fixup_irqs NULL
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#endif
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