Maxime Ripard 601cb6d573 clk: socfpga: gate: Account for the divider in determine_rate ... Commit 9607beb917 ("clk: socfpga: gate: Add a determine_rate hook") added a determine_rate implementation set to the clk_hw_determine_rate_no_reparent, but failed to account for the internal divider that wasn't used before anywhere but in recalc_rate. This led to inconsistencies between the clock rate stored in clk_core->rate and the one returned by clk_round_rate() that leverages determine_rate(). Since that driver seems to be widely used (and thus regression-prone) and not supporting rate changes (since it's missing a .set_rate implementation), we can just report the current divider programmed in the clock but not try to change it in any way. This should be good enough to fix the issues reported, and if someone ever wants to allow the divider to change then it should be easy enough using the clk-divider helpers. Link: https://lore.kernel.org/linux-clk/20231005095927.12398-2-b.spranger@linutronix.de/ Fixes: 9607beb917 ("clk: socfpga: gate: Add a determine_rate hook") Reported-by: Benedikt Spranger <b.spranger@linutronix.de> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20231012083729.2148044-1-mripard@kernel.org [sboyd@kernel.org: Fix hw -> hwclk] Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2023-10-12 17:30:54 -07:00
..
Kconfig	clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)	2021-03-23 11:03:36 -05:00
Makefile	clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)	2021-03-23 11:03:36 -05:00
clk-agilex.c	clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()	2023-08-22 14:28:34 -07:00
clk-gate-a10.c	clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling	2023-03-21 16:47:48 -07:00
clk-gate-s10.c	clk: cleanup comments	2022-03-11 18:22:15 -08:00
clk-gate.c	clk: socfpga: gate: Account for the divider in determine_rate	2023-10-12 17:30:54 -07:00
clk-periph-a10.c	clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling	2023-03-21 16:47:48 -07:00
clk-periph-s10.c	clk: socfpga: cleanup spdx tags	2022-03-11 18:21:45 -08:00
clk-periph.c	clk: socfpga: use of_clk_add_hw_provider and improve error handling	2023-03-21 16:47:48 -07:00
clk-pll-a10.c	clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling	2023-03-21 16:47:48 -07:00
clk-pll-s10.c	clk: socfpga: cleanup spdx tags	2022-03-11 18:21:45 -08:00
clk-pll.c	clk: socfpga: use of_clk_add_hw_provider and improve error handling	2023-03-21 16:47:48 -07:00
clk-s10.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
clk.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13	2019-05-21 11:28:45 +02:00
clk.h	clk: socfpga: remove the setting of clk-phase for sdmmc_clk	2022-12-07 13:22:37 +01:00
stratix10-clk.h	clk: agilex/stratix10: add support for the 2nd bypass	2021-06-27 16:39:59 -07:00