293 lines
12 KiB
C
293 lines
12 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* GPU doorbell structures, functions & helpers
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*/
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struct amdgpu_doorbell {
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/* doorbell mmio */
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resource_size_t base;
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resource_size_t size;
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u32 __iomem *ptr;
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u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
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};
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/* Reserved doorbells for amdgpu (including multimedia).
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* KFD can use all the rest in the 2M doorbell bar.
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* For asic before vega10, doorbell is 32-bit, so the
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* index/offset is in dword. For vega10 and after, doorbell
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* can be 64-bit, so the index defined is in qword.
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*/
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struct amdgpu_doorbell_index {
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uint32_t kiq;
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uint32_t mec_ring0;
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uint32_t mec_ring1;
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uint32_t mec_ring2;
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uint32_t mec_ring3;
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uint32_t mec_ring4;
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uint32_t mec_ring5;
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uint32_t mec_ring6;
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uint32_t mec_ring7;
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uint32_t userqueue_start;
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uint32_t userqueue_end;
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uint32_t gfx_ring0;
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uint32_t gfx_ring1;
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uint32_t sdma_engine[8];
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uint32_t ih;
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union {
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struct {
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uint32_t vcn_ring0_1;
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uint32_t vcn_ring2_3;
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uint32_t vcn_ring4_5;
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uint32_t vcn_ring6_7;
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} vcn;
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struct {
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uint32_t uvd_ring0_1;
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uint32_t uvd_ring2_3;
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uint32_t uvd_ring4_5;
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uint32_t uvd_ring6_7;
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uint32_t vce_ring0_1;
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uint32_t vce_ring2_3;
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uint32_t vce_ring4_5;
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uint32_t vce_ring6_7;
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} uvd_vce;
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};
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uint32_t first_non_cp;
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uint32_t last_non_cp;
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uint32_t max_assignment;
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/* Per engine SDMA doorbell size in dword */
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uint32_t sdma_doorbell_range;
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};
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typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
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{
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AMDGPU_DOORBELL_KIQ = 0x000,
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AMDGPU_DOORBELL_HIQ = 0x001,
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AMDGPU_DOORBELL_DIQ = 0x002,
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AMDGPU_DOORBELL_MEC_RING0 = 0x010,
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AMDGPU_DOORBELL_MEC_RING1 = 0x011,
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AMDGPU_DOORBELL_MEC_RING2 = 0x012,
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AMDGPU_DOORBELL_MEC_RING3 = 0x013,
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AMDGPU_DOORBELL_MEC_RING4 = 0x014,
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AMDGPU_DOORBELL_MEC_RING5 = 0x015,
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AMDGPU_DOORBELL_MEC_RING6 = 0x016,
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AMDGPU_DOORBELL_MEC_RING7 = 0x017,
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AMDGPU_DOORBELL_GFX_RING0 = 0x020,
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AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
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AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
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AMDGPU_DOORBELL_IH = 0x1E8,
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AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
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AMDGPU_DOORBELL_INVALID = 0xFFFF
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} AMDGPU_DOORBELL_ASSIGNMENT;
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typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
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{
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/* Compute + GFX: 0~255 */
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AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
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AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
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AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
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AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
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AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
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AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
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AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
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AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
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AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
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AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
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AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
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AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
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AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
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AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
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/* SDMA:256~335*/
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A,
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E,
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128,
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C,
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AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146,
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/* IH: 376~391 */
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AMDGPU_VEGA20_DOORBELL_IH = 0x178,
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/* MMSCH: 392~407
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* overlap the doorbell assignment with VCN as they are mutually exclusive
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* VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
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*/
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AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */
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AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
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AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
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AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
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AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */
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AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D,
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AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E,
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AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F,
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AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
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AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
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AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
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AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
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AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
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AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
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AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
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AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
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AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
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AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
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AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
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AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
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} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
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typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
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{
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/* Compute + GFX: 0~255 */
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AMDGPU_NAVI10_DOORBELL_KIQ = 0x000,
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AMDGPU_NAVI10_DOORBELL_HIQ = 0x001,
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AMDGPU_NAVI10_DOORBELL_DIQ = 0x002,
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AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003,
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AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004,
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AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005,
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AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006,
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AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007,
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AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008,
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AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009,
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AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A,
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AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00B,
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AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A,
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AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B,
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AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C,
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/* SDMA:256~335*/
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AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100,
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AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A,
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/* IH: 376~391 */
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AMDGPU_NAVI10_DOORBELL_IH = 0x178,
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/* MMSCH: 392~407
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* overlap the doorbell assignment with VCN as they are mutually exclusive
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* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
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*/
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AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
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AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189,
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AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A,
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AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B,
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AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
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AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCN6_7,
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AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F,
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AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF
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} AMDGPU_NAVI10_DOORBELL_ASSIGNMENT;
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/*
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* 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
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*/
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typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
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{
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/*
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* All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
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* a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
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* Compute related doorbells are allocated from 0x00 to 0x8a
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*/
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/* kernel scheduling */
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AMDGPU_DOORBELL64_KIQ = 0x00,
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/* HSA interface queue and debug queue */
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AMDGPU_DOORBELL64_HIQ = 0x01,
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AMDGPU_DOORBELL64_DIQ = 0x02,
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/* Compute engines */
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AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
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AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
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AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
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AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
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AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
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AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
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AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
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AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
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/* User queue doorbell range (128 doorbells) */
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AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
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AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
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/* Graphics engine */
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AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
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/*
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* Other graphics doorbells can be allocated here: from 0x8c to 0xdf
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* Graphics voltage island aperture 1
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* default non-graphics QWORD index is 0xe0 - 0xFF inclusive
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*/
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/* For vega10 sriov, the sdma doorbell must be fixed as follow
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* to keep the same setting with host driver, or it will
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* happen conflicts
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*/
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AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
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AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
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/* Interrupt handler */
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AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
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AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
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AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
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/* VCN engine use 32 bits doorbell */
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AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
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AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
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AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
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AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
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/* overlap the doorbell assignment with VCN as they are mutually exclusive
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* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
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*/
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AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
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AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
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AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
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AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
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AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
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AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
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AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
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AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
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AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0,
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AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
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AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
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AMDGPU_DOORBELL64_INVALID = 0xFFFF
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} AMDGPU_DOORBELL64_ASSIGNMENT;
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u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
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void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
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u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
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void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
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#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
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#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
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#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
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#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
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