467 lines
14 KiB
C
467 lines
14 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "atomfirmware.h"
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#include "amdgpu_atomfirmware.h"
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#include "atom.h"
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#include "atombios.h"
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bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
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{
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int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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firmwareinfo);
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uint16_t data_offset;
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if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
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NULL, NULL, &data_offset)) {
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struct atom_firmware_info_v3_1 *firmware_info =
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(struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
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data_offset);
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if (le32_to_cpu(firmware_info->firmware_capability) &
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ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
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return true;
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}
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return false;
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}
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void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
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{
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int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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firmwareinfo);
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uint16_t data_offset;
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if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
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NULL, NULL, &data_offset)) {
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struct atom_firmware_info_v3_1 *firmware_info =
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(struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
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data_offset);
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adev->bios_scratch_reg_offset =
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le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
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}
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}
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int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
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{
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struct atom_context *ctx = adev->mode_info.atom_context;
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int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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vram_usagebyfirmware);
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struct vram_usagebyfirmware_v2_1 * firmware_usage;
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uint32_t start_addr, size;
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uint16_t data_offset;
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int usage_bytes = 0;
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if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
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firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
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DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
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le32_to_cpu(firmware_usage->start_address_in_kb),
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le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
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le16_to_cpu(firmware_usage->used_by_driver_in_kb));
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start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
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size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
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if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
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(uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
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ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
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/* Firmware request VRAM reservation for SR-IOV */
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adev->fw_vram_usage.start_offset = (start_addr &
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(~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
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adev->fw_vram_usage.size = size << 10;
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/* Use the default scratch size */
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usage_bytes = 0;
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} else {
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usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
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}
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}
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ctx->scratch_size_bytes = 0;
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if (usage_bytes == 0)
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usage_bytes = 20 * 1024;
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/* allocate some scratch memory */
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ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
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if (!ctx->scratch)
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return -ENOMEM;
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ctx->scratch_size_bytes = usage_bytes;
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return 0;
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}
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union igp_info {
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struct atom_integrated_system_info_v1_11 v11;
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};
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union umc_info {
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struct atom_umc_info_v3_1 v31;
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};
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union vram_info {
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struct atom_vram_info_header_v2_3 v23;
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struct atom_vram_info_header_v2_4 v24;
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};
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/*
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* Return vram width from integrated system info table, if available,
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* or 0 if not.
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*/
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int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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int index;
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u16 data_offset, size;
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union igp_info *igp_info;
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union vram_info *vram_info;
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u32 mem_channel_number;
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u32 mem_channel_width;
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u8 frev, crev;
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if (adev->flags & AMD_IS_APU)
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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integratedsysteminfo);
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else
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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vram_info);
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/* get any igp specific overrides */
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if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
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&frev, &crev, &data_offset)) {
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if (adev->flags & AMD_IS_APU) {
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igp_info = (union igp_info *)
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(mode_info->atom_context->bios + data_offset);
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switch (crev) {
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case 11:
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mem_channel_number = igp_info->v11.umachannelnumber;
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/* channel width is 64 */
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return mem_channel_number * 64;
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default:
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return 0;
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}
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} else {
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vram_info = (union vram_info *)
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(mode_info->atom_context->bios + data_offset);
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switch (crev) {
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case 3:
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mem_channel_number = vram_info->v23.vram_module[0].channel_num;
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mem_channel_width = vram_info->v23.vram_module[0].channel_width;
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return mem_channel_number * (1 << mem_channel_width);
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case 4:
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mem_channel_number = vram_info->v24.vram_module[0].channel_num;
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mem_channel_width = vram_info->v24.vram_module[0].channel_width;
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return mem_channel_number * (1 << mem_channel_width);
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default:
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return 0;
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}
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}
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}
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return 0;
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}
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static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
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int atom_mem_type)
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{
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int vram_type;
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if (adev->flags & AMD_IS_APU) {
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switch (atom_mem_type) {
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case Ddr2MemType:
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case LpDdr2MemType:
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vram_type = AMDGPU_VRAM_TYPE_DDR2;
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break;
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case Ddr3MemType:
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case LpDdr3MemType:
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vram_type = AMDGPU_VRAM_TYPE_DDR3;
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break;
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case Ddr4MemType:
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case LpDdr4MemType:
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vram_type = AMDGPU_VRAM_TYPE_DDR4;
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break;
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default:
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vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
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break;
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}
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} else {
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switch (atom_mem_type) {
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case ATOM_DGPU_VRAM_TYPE_GDDR5:
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vram_type = AMDGPU_VRAM_TYPE_GDDR5;
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break;
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case ATOM_DGPU_VRAM_TYPE_HBM2:
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vram_type = AMDGPU_VRAM_TYPE_HBM;
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break;
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case ATOM_DGPU_VRAM_TYPE_GDDR6:
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vram_type = AMDGPU_VRAM_TYPE_GDDR6;
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break;
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default:
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vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
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break;
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}
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}
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return vram_type;
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}
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/*
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* Return vram type from either integrated system info table
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* or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
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*/
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int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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int index;
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u16 data_offset, size;
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union igp_info *igp_info;
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union vram_info *vram_info;
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u8 frev, crev;
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u8 mem_type;
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if (adev->flags & AMD_IS_APU)
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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integratedsysteminfo);
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else
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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vram_info);
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if (amdgpu_atom_parse_data_header(mode_info->atom_context,
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index, &size,
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&frev, &crev, &data_offset)) {
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if (adev->flags & AMD_IS_APU) {
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igp_info = (union igp_info *)
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(mode_info->atom_context->bios + data_offset);
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switch (crev) {
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case 11:
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mem_type = igp_info->v11.memorytype;
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return convert_atom_mem_type_to_vram_type(adev, mem_type);
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default:
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return 0;
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}
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} else {
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vram_info = (union vram_info *)
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(mode_info->atom_context->bios + data_offset);
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switch (crev) {
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case 3:
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mem_type = vram_info->v23.vram_module[0].memory_type;
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return convert_atom_mem_type_to_vram_type(adev, mem_type);
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case 4:
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mem_type = vram_info->v24.vram_module[0].memory_type;
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return convert_atom_mem_type_to_vram_type(adev, mem_type);
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default:
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return 0;
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}
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}
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}
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return 0;
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}
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/*
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* Return true if vbios enabled ecc by default, if umc info table is available
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* or false if ecc is not enabled or umc info table is not available
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*/
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bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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int index;
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u16 data_offset, size;
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union umc_info *umc_info;
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u8 frev, crev;
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bool ecc_default_enabled = false;
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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umc_info);
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if (amdgpu_atom_parse_data_header(mode_info->atom_context,
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index, &size, &frev, &crev, &data_offset)) {
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/* support umc_info 3.1+ */
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if ((frev == 3 && crev >= 1) || (frev > 3)) {
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umc_info = (union umc_info *)
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(mode_info->atom_context->bios + data_offset);
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ecc_default_enabled =
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(le32_to_cpu(umc_info->v31.umc_config) &
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UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
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}
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}
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return ecc_default_enabled;
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}
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union firmware_info {
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struct atom_firmware_info_v3_1 v31;
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};
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/*
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* Return true if vbios supports sram ecc or false if not
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*/
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bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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int index;
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u16 data_offset, size;
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union firmware_info *firmware_info;
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u8 frev, crev;
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bool sram_ecc_supported = false;
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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firmwareinfo);
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if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
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index, &size, &frev, &crev, &data_offset)) {
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/* support firmware_info 3.1 + */
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if ((frev == 3 && crev >=1) || (frev > 3)) {
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firmware_info = (union firmware_info *)
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(mode_info->atom_context->bios + data_offset);
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sram_ecc_supported =
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(le32_to_cpu(firmware_info->v31.firmware_capability) &
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ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
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}
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}
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return sram_ecc_supported;
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}
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union smu_info {
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struct atom_smu_info_v3_1 v31;
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};
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int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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struct amdgpu_pll *spll = &adev->clock.spll;
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struct amdgpu_pll *mpll = &adev->clock.mpll;
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uint8_t frev, crev;
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uint16_t data_offset;
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int ret = -EINVAL, index;
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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firmwareinfo);
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if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
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&frev, &crev, &data_offset)) {
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union firmware_info *firmware_info =
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(union firmware_info *)(mode_info->atom_context->bios +
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data_offset);
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adev->clock.default_sclk =
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le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
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adev->clock.default_mclk =
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le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
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adev->pm.current_sclk = adev->clock.default_sclk;
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adev->pm.current_mclk = adev->clock.default_mclk;
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/* not technically a clock, but... */
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adev->mode_info.firmware_flags =
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le32_to_cpu(firmware_info->v31.firmware_capability);
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ret = 0;
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}
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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smu_info);
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if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
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&frev, &crev, &data_offset)) {
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union smu_info *smu_info =
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(union smu_info *)(mode_info->atom_context->bios +
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data_offset);
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/* system clock */
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spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
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spll->reference_div = 0;
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spll->min_post_div = 1;
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spll->max_post_div = 1;
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spll->min_ref_div = 2;
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spll->max_ref_div = 0xff;
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spll->min_feedback_div = 4;
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spll->max_feedback_div = 0xff;
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spll->best_vco = 0;
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ret = 0;
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}
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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umc_info);
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if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
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&frev, &crev, &data_offset)) {
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union umc_info *umc_info =
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(union umc_info *)(mode_info->atom_context->bios +
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data_offset);
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/* memory clock */
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mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
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mpll->reference_div = 0;
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mpll->min_post_div = 1;
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mpll->max_post_div = 1;
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mpll->min_ref_div = 2;
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mpll->max_ref_div = 0xff;
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mpll->min_feedback_div = 4;
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mpll->max_feedback_div = 0xff;
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mpll->best_vco = 0;
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ret = 0;
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}
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return ret;
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}
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union gfx_info {
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struct atom_gfx_info_v2_4 v24;
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};
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int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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int index;
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uint8_t frev, crev;
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uint16_t data_offset;
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index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
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gfx_info);
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if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
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&frev, &crev, &data_offset)) {
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union gfx_info *gfx_info = (union gfx_info *)
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(mode_info->atom_context->bios + data_offset);
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switch (crev) {
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case 4:
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adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
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adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
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adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
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adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
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adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
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adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
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adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
|
|
adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
|
|
adev->gfx.config.gs_prim_buffer_depth =
|
|
le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
|
|
adev->gfx.config.double_offchip_lds_buf =
|
|
gfx_info->v24.gc_double_offchip_lds_buffer;
|
|
adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
|
|
adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
|
|
adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
|
|
adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
}
|
|
return -EINVAL;
|
|
}
|