814 lines
18 KiB
Plaintext
814 lines
18 KiB
Plaintext
/*
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* DTS file for CSR SiRFatlas7 SoC
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*
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* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "sirf,atlas7";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial9 = &usp2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <1>;
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};
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};
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noc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x10000000 0x10000000 0xc0000000>;
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gic: interrupt-controller@10301000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x10301000 0x1000>,
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<0x10302000 0x0100>;
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};
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pmu_regulator: pmu_regulator@10E30020 {
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compatible = "sirf,atlas7-pmu-ldo";
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reg = <0x10E30020 0x4>;
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ldo: ldo {
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regulator-name = "ldo";
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};
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};
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atlas7_codec: atlas7_codec@10E30000 {
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#sound-dai-cells = <0>;
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compatible = "sirf,atlas7-codec";
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reg = <0x10E30000 0x400>;
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clocks = <&car 62>;
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ldo-supply = <&ldo>;
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};
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atlas7_iacc: atlas7_iacc@10D01000 {
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#sound-dai-cells = <0>;
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compatible = "sirf,atlas7-iacc";
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reg = <0x10D01000 0x100>;
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dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
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<&dmac3 3>, <&dmac3 9>;
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dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
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clocks = <&car 62>;
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};
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ipc@13240000 {
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compatible = "sirf,atlas7-ipc";
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ranges = <0x13240000 0x13240000 0x00010000>;
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#address-cells = <1>;
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#size-cells = <1>;
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hwspinlock {
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compatible = "sirf,hwspinlock";
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reg = <0x13240000 0x00010000>;
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num-spinlocks = <30>;
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};
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ns_m3_rproc@0 {
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compatible = "sirf,ns2m30-rproc";
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reg = <0x13240000 0x00010000>;
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interrupts = <0 123 0>;
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};
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ns_m3_rproc@1 {
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compatible = "sirf,ns2m31-rproc";
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reg = <0x13240000 0x00010000>;
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interrupts = <0 126 0>;
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};
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ns_kal_rproc@0 {
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compatible = "sirf,ns2kal0-rproc";
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reg = <0x13240000 0x00010000>;
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interrupts = <0 124 0>;
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};
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ns_kal_rproc@1 {
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compatible = "sirf,ns2kal1-rproc";
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reg = <0x13240000 0x00010000>;
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interrupts = <0 127 0>;
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};
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};
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pinctrl: ioc@18880000 {
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compatible = "sirf,atlas7-ioc";
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reg = <0x18880000 0x1000>,
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<0x10E40000 0x1000>;
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};
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pmipc {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x13240000 0x13240000 0x00010000>;
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pmipc@0x13240000 {
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compatible = "sirf,atlas7-pmipc";
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reg = <0x13240000 0x00010000>;
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};
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};
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dramfw {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x10830000 0x10830000 0x18000>;
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dramfw@10820000 {
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compatible = "sirf,nocfw-dramfw";
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reg = <0x10830000 0x18000>;
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};
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};
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spramfw {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x10250000 0x10250000 0x3000>;
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spramfw@10820000 {
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compatible = "sirf,nocfw-spramfw";
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reg = <0x10250000 0x3000>;
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};
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};
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cpum {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x10200000 0x10200000 0x3000>;
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cpum@10200000 {
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compatible = "sirf,nocfw-cpum";
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reg = <0x10200000 0x3000>;
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};
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};
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cgum {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x18641000 0x18641000 0x3000>,
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<0x18620000 0x18620000 0x1000>;
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cgum@18641000 {
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compatible = "sirf,nocfw-cgum";
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reg = <0x18641000 0x3000>;
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};
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car: clock-controller@18620000 {
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compatible = "sirf,atlas7-car";
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reg = <0x18620000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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gnssm {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x18000000 0x18000000 0x0000ffff>,
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<0x18010000 0x18010000 0x1000>,
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<0x18020000 0x18020000 0x1000>,
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<0x18030000 0x18030000 0x1000>,
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<0x18040000 0x18040000 0x1000>,
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<0x18050000 0x18050000 0x1000>,
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<0x18060000 0x18060000 0x1000>,
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<0x18100000 0x18100000 0x3000>,
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<0x18250000 0x18250000 0x10000>,
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<0x18200000 0x18200000 0x1000>;
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dmac0: dma-controller@18000000 {
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cell-index = <0>;
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compatible = "sirf,atlas7-dmac";
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reg = <0x18000000 0x1000>;
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interrupts = <0 12 0>;
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clocks = <&car 89>;
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dma-channels = <16>;
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#dma-cells = <1>;
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};
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gnssmfw@0x18100000 {
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compatible = "sirf,nocfw-gnssm";
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reg = <0x18100000 0x3000>;
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};
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uart0: uart@18010000 {
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cell-index = <0>;
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compatible = "sirf,atlas7-uart";
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reg = <0x18010000 0x1000>;
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interrupts = <0 17 0>;
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clocks = <&car 90>;
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fifosize = <128>;
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dmas = <&dmac0 3>, <&dmac0 2>;
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dma-names = "rx", "tx";
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};
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uart1: uart@18020000 {
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cell-index = <1>;
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compatible = "sirf,atlas7-uart";
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reg = <0x18020000 0x1000>;
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interrupts = <0 18 0>;
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clocks = <&car 88>;
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fifosize = <32>;
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};
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uart2: uart@18030000 {
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cell-index = <2>;
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compatible = "sirf,atlas7-uart";
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reg = <0x18030000 0x1000>;
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interrupts = <0 19 0>;
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clocks = <&car 91>;
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fifosize = <128>;
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dmas = <&dmac0 6>, <&dmac0 7>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart3: uart@18040000 {
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cell-index = <3>;
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compatible = "sirf,atlas7-uart";
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reg = <0x18040000 0x1000>;
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interrupts = <0 66 0>;
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clocks = <&car 92>;
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fifosize = <128>;
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dmas = <&dmac0 4>, <&dmac0 5>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart4: uart@18050000 {
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cell-index = <4>;
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compatible = "sirf,atlas7-uart";
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reg = <0x18050000 0x1000>;
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interrupts = <0 69 0>;
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clocks = <&car 93>;
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fifosize = <128>;
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dmas = <&dmac0 0>, <&dmac0 1>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart5: uart@18060000 {
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cell-index = <5>;
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compatible = "sirf,atlas7-uart";
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reg = <0x18060000 0x1000>;
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interrupts = <0 71 0>;
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clocks = <&car 94>;
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fifosize = <128>;
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dmas = <&dmac0 8>, <&dmac0 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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dspub@18250000 {
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compatible = "dx,cc44p";
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reg = <0x18250000 0x10000>;
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interrupts = <0 27 0>;
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};
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spi1: spi@18200000 {
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compatible = "sirf,prima2-spi";
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reg = <0x18200000 0x1000>;
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interrupts = <0 16 0>;
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clocks = <&car 95>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&dmac0 12>, <&dmac0 13>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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};
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gpum {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x13000000 0x13000000 0x3000>;
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gpum@0x13000000 {
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compatible = "sirf,nocfw-gpum";
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reg = <0x13000000 0x3000>;
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};
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};
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mediam {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x16000000 0x16000000 0x00200000>,
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<0x17020000 0x17020000 0x1000>,
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<0x17030000 0x17030000 0x1000>,
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<0x17040000 0x17040000 0x1000>,
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<0x17050000 0x17050000 0x10000>,
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<0x17060000 0x17060000 0x200>,
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<0x17060200 0x17060200 0x100>,
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<0x17070000 0x17070000 0x200>,
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<0x17070200 0x17070200 0x100>,
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<0x170A0000 0x170A0000 0x3000>;
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mediam@170A0000 {
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compatible = "sirf,nocfw-mediam";
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reg = <0x170A0000 0x3000>;
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};
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gpio_0: gpio_mediam@17040000 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "sirf,atlas7-gpio";
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reg = <0x17040000 0x1000>;
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interrupts = <0 13 0>, <0 14 0>;
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clocks = <&car 107>;
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clock-names = "gpio0_io";
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gpio-controller;
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interrupt-controller;
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};
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nand@17050000 {
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compatible = "sirf,atlas7-nand";
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reg = <0x17050000 0x10000>;
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interrupts = <0 41 0>;
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clocks = <&car 108>, <&car 112>;
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clock-names = "nand_io", "nand_nand";
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};
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sd0: sdhci@16000000 {
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cell-index = <0>;
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compatible = "sirf,atlas7-sdhc";
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reg = <0x16000000 0x100000>;
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interrupts = <0 38 0>;
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clocks = <&car 109>, <&car 111>;
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clock-names = "core", "iface";
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wp-inverted;
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non-removable;
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status = "disabled";
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bus-width = <8>;
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};
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sd1: sdhci@16100000 {
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cell-index = <1>;
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compatible = "sirf,atlas7-sdhc";
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reg = <0x16100000 0x100000>;
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interrupts = <0 38 0>;
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clocks = <&car 109>, <&car 111>;
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clock-names = "core", "iface";
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non-removable;
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status = "disabled";
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bus-width = <8>;
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};
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usb0: usb@17060000 {
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cell-index = <0>;
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compatible = "sirf,atlas7-usb";
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reg = <0x17060000 0x200>;
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interrupts = <0 10 0>;
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clocks = <&car 113>;
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sirf,usbphy = <&usbphy0>;
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phy_type = "utmi";
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dr_mode = "otg";
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maximum-speed = "high-speed";
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status = "okay";
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};
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usb1: usb@17070000 {
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cell-index = <1>;
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compatible = "sirf,atlas7-usb";
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reg = <0x17070000 0x200>;
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interrupts = <0 11 0>;
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clocks = <&car 114>;
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sirf,usbphy = <&usbphy1>;
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phy_type = "utmi";
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dr_mode = "host";
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maximum-speed = "high-speed";
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status = "okay";
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};
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usbphy0: usbphy@0 {
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compatible = "sirf,atlas7-usbphy";
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reg = <0x17060200 0x100>;
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clocks = <&car 115>;
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status = "okay";
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};
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usbphy1: usbphy@1 {
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compatible = "sirf,atlas7-usbphy";
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reg = <0x17070200 0x100>;
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clocks = <&car 116>;
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status = "okay";
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};
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i2c0: i2c@17020000 {
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cell-index = <0>;
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compatible = "sirf,prima2-i2c";
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reg = <0x17020000 0x1000>;
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interrupts = <0 24 0>;
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clocks = <&car 105>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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vdifm {
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compatible = "arteris, flexnoc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x13290000 0x13290000 0x3000>,
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<0x13300000 0x13300000 0x1000>,
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<0x14200000 0x14200000 0x600000>;
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vdifm@13290000 {
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compatible = "sirf,nocfw-vdifm";
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reg = <0x13290000 0x3000>;
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};
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gpio_1: gpio_vdifm@13300000 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "sirf,atlas7-gpio";
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reg = <0x13300000 0x1000>;
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interrupts = <0 43 0>, <0 44 0>, <0 45 0>;
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clocks = <&car 84>;
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clock-names = "gpio1_io";
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gpio-controller;
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interrupt-controller;
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};
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sd2: sdhci@14200000 {
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cell-index = <2>;
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compatible = "sirf,atlas7-sdhc";
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reg = <0x14200000 0x100000>;
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interrupts = <0 23 0>;
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clocks = <&car 70>, <&car 75>;
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clock-names = "core", "iface";
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status = "disabled";
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bus-width = <4>;
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sd-uhs-sdr50;
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vqmmc-supply = <&vqmmc>;
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vqmmc: vqmmc@2 {
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-name = "vqmmc-ldo";
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regulator-type = "voltage";
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regulator-boot-on;
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regulator-allow-bypass;
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};
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};
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sd3: sdhci@14300000 {
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cell-index = <3>;
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compatible = "sirf,atlas7-sdhc";
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reg = <0x14300000 0x100000>;
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interrupts = <0 23 0>;
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clocks = <&car 76>, <&car 81>;
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clock-names = "core", "iface";
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status = "disabled";
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bus-width = <4>;
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};
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sd5: sdhci@14500000 {
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cell-index = <5>;
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compatible = "sirf,atlas7-sdhc";
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reg = <0x14500000 0x100000>;
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interrupts = <0 39 0>;
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clocks = <&car 71>, <&car 76>;
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clock-names = "core", "iface";
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status = "disabled";
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bus-width = <4>;
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loop-dma;
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};
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sd6: sdhci@14600000 {
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cell-index = <6>;
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compatible = "sirf,atlas7-sdhc";
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reg = <0x14600000 0x100000>;
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interrupts = <0 98 0>;
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clocks = <&car 72>, <&car 77>;
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clock-names = "core", "iface";
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status = "disabled";
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bus-width = <4>;
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};
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sd7: sdhci@14700000 {
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cell-index = <7>;
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|
compatible = "sirf,atlas7-sdhc";
|
|
reg = <0x14700000 0x100000>;
|
|
interrupts = <0 98 0>;
|
|
clocks = <&car 72>, <&car 77>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
bus-width = <4>;
|
|
};
|
|
};
|
|
|
|
audiom {
|
|
compatible = "arteris, flexnoc", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x10d50000 0x10d50000 0x0000ffff>,
|
|
<0x10d60000 0x10d60000 0x0000ffff>,
|
|
<0x10d80000 0x10d80000 0x0000ffff>,
|
|
<0x10d90000 0x10d90000 0x0000ffff>,
|
|
<0x10ED0000 0x10ED0000 0x3000>,
|
|
<0x10dc8000 0x10dc8000 0x1000>,
|
|
<0x10dc0000 0x10dc0000 0x1000>,
|
|
<0x10db0000 0x10db0000 0x4000>,
|
|
<0x10d40000 0x10d40000 0x1000>,
|
|
<0x10d30000 0x10d30000 0x1000>;
|
|
|
|
timer@10dc0000 {
|
|
compatible = "sirf,atlas7-tick";
|
|
reg = <0x10dc0000 0x1000>;
|
|
interrupts = <0 0 0>,
|
|
<0 1 0>,
|
|
<0 2 0>,
|
|
<0 49 0>,
|
|
<0 50 0>,
|
|
<0 51 0>;
|
|
clocks = <&car 47>;
|
|
};
|
|
|
|
timerb@10dc8000 {
|
|
compatible = "sirf,atlas7-tick";
|
|
reg = <0x10dc8000 0x1000>;
|
|
interrupts = <0 74 0>,
|
|
<0 75 0>,
|
|
<0 76 0>,
|
|
<0 77 0>,
|
|
<0 78 0>,
|
|
<0 79 0>;
|
|
clocks = <&car 47>;
|
|
};
|
|
|
|
vip0@10db0000 {
|
|
compatible = "sirf,atlas7-vip0";
|
|
reg = <0x10db0000 0x2000>;
|
|
interrupts = <0 85 0>;
|
|
sirf,vip_cma_size = <0xC00000>;
|
|
};
|
|
|
|
cvd@10db2000 {
|
|
compatible = "sirf,cvd";
|
|
reg = <0x10db2000 0x2000>;
|
|
clocks = <&car 46>;
|
|
};
|
|
|
|
dmac2: dma-controller@10d50000 {
|
|
cell-index = <2>;
|
|
compatible = "sirf,atlas7-dmac";
|
|
reg = <0x10d50000 0xffff>;
|
|
interrupts = <0 55 0>;
|
|
clocks = <&car 60>;
|
|
dma-channels = <16>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
dmac3: dma-controller@10d60000 {
|
|
cell-index = <3>;
|
|
compatible = "sirf,atlas7-dmac";
|
|
reg = <0x10d60000 0xffff>;
|
|
interrupts = <0 56 0>;
|
|
clocks = <&car 61>;
|
|
dma-channels = <16>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
adc: adc@10d80000 {
|
|
compatible = "sirf,atlas7-adc";
|
|
reg = <0x10d80000 0xffff>;
|
|
interrupts = <0 34 0>;
|
|
clocks = <&car 49>;
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
pulsec@10d90000 {
|
|
compatible = "sirf,prima2-pulsec";
|
|
reg = <0x10d90000 0xffff>;
|
|
interrupts = <0 42 0>;
|
|
clocks = <&car 54>;
|
|
};
|
|
|
|
audiom@10ED0000 {
|
|
compatible = "sirf,nocfw-audiom";
|
|
reg = <0x10ED0000 0x3000>;
|
|
interrupts = <0 102 0>;
|
|
};
|
|
|
|
usp1: usp@10d30000 {
|
|
cell-index = <1>;
|
|
reg = <0x10d30000 0x1000>;
|
|
fifosize = <512>;
|
|
clocks = <&car 58>;
|
|
dmas = <&dmac2 6>, <&dmac2 7>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
usp2: usp@10d40000 {
|
|
cell-index = <2>;
|
|
reg = <0x10d40000 0x1000>;
|
|
interrupts = <0 22 0>;
|
|
clocks = <&car 59>;
|
|
dmas = <&dmac2 12>, <&dmac2 13>;
|
|
dma-names = "rx", "tx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ddrm {
|
|
compatible = "arteris, flexnoc", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x10820000 0x10820000 0x3000>,
|
|
<0x10800000 0x10800000 0x2000>;
|
|
ddrm@10820000 {
|
|
compatible = "sirf,nocfw-ddrm";
|
|
reg = <0x10820000 0x3000>;
|
|
interrupts = <0 105 0>;
|
|
};
|
|
|
|
memory-controller@0x10800000 {
|
|
compatible = "sirf,atlas7-memc";
|
|
reg = <0x10800000 0x2000>;
|
|
};
|
|
|
|
};
|
|
|
|
btm {
|
|
compatible = "arteris, flexnoc", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x11002000 0x11002000 0x0000ffff>,
|
|
<0x11010000 0x11010000 0x3000>,
|
|
<0x11000000 0x11000000 0x1000>,
|
|
<0x11001000 0x11001000 0x1000>;
|
|
|
|
dmac4: dma-controller@11002000 {
|
|
cell-index = <4>;
|
|
compatible = "sirf,atlas7-dmac";
|
|
reg = <0x11002000 0x1000>;
|
|
interrupts = <0 99 0>;
|
|
clocks = <&car 130>;
|
|
dma-channels = <16>;
|
|
#dma-cells = <1>;
|
|
};
|
|
uart6: uart@11000000 {
|
|
cell-index = <6>;
|
|
compatible = "sirf,atlas7-bt-uart",
|
|
"sirf,atlas7-uart";
|
|
reg = <0x11000000 0x1000>;
|
|
interrupts = <0 100 0>;
|
|
clocks = <&car 131>, <&car 133>, <&car 134>;
|
|
clock-names = "uart", "general", "noc";
|
|
fifosize = <128>;
|
|
dmas = <&dmac4 12>, <&dmac4 13>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
usp3: usp@11001000 {
|
|
compatible = "sirf,atlas7-bt-usp",
|
|
"sirf,prima2-usp-pcm";
|
|
cell-index = <3>;
|
|
reg = <0x11001000 0x1000>;
|
|
fifosize = <512>;
|
|
clocks = <&car 132>, <&car 129>, <&car 133>,
|
|
<&car 134>, <&car 135>;
|
|
clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
|
|
"noc_btm_io", "thbtm_io";
|
|
dmas = <&dmac4 0>, <&dmac4 1>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
btm@11010000 {
|
|
compatible = "sirf,nocfw-btm";
|
|
reg = <0x11010000 0x3000>;
|
|
};
|
|
};
|
|
|
|
rtcm {
|
|
compatible = "arteris, flexnoc", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x18810000 0x18810000 0x3000>,
|
|
<0x18840000 0x18840000 0x1000>,
|
|
<0x18890000 0x18890000 0x1000>,
|
|
<0x188B0000 0x188B0000 0x10000>,
|
|
<0x188D0000 0x188D0000 0x1000>;
|
|
rtcm@18810000 {
|
|
compatible = "sirf,nocfw-rtcm";
|
|
reg = <0x18810000 0x3000>;
|
|
interrupts = <0 109 0>;
|
|
};
|
|
|
|
gpio_2: gpio_rtcm@18890000 {
|
|
#gpio-cells = <2>;
|
|
#interrupt-cells = <2>;
|
|
compatible = "sirf,atlas7-gpio";
|
|
reg = <0x18890000 0x1000>;
|
|
interrupts = <0 47 0>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
};
|
|
|
|
rtc-iobg@18840000 {
|
|
compatible = "sirf,prima2-rtciobg",
|
|
"sirf-prima2-rtciobg-bus",
|
|
"simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x18840000 0x1000>;
|
|
|
|
sysrtc@2000 {
|
|
compatible = "sirf,prima2-sysrtc";
|
|
reg = <0x2000 0x100>;
|
|
interrupts = <0 52 0>;
|
|
};
|
|
pwrc@3000 {
|
|
compatible = "sirf,atlas7-pwrc";
|
|
reg = <0x3000 0x100>;
|
|
};
|
|
};
|
|
|
|
qspi: flash@188B0000 {
|
|
cell-index = <0>;
|
|
compatible = "sirf,atlas7-qspi-nor";
|
|
reg = <0x188B0000 0x10000>;
|
|
interrupts = <0 15 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
retain@0x188D0000 {
|
|
compatible = "sirf,atlas7-retain";
|
|
reg = <0x188D0000 0x1000>;
|
|
};
|
|
|
|
};
|
|
disp-iobg {
|
|
/* lcdc0 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x13100000 0x13100000 0x20000>,
|
|
<0x10e10000 0x10e10000 0x10000>;
|
|
|
|
lcd@13100000 {
|
|
compatible = "sirf,atlas7-lcdc";
|
|
reg = <0x13100000 0x10000>;
|
|
interrupts = <0 30 0>;
|
|
clocks = <&car 79>;
|
|
};
|
|
vpp@13110000 {
|
|
compatible = "sirf,atlas7-vpp";
|
|
reg = <0x13110000 0x10000>;
|
|
interrupts = <0 31 0>;
|
|
clocks = <&car 78>;
|
|
resets = <&car 29>;
|
|
};
|
|
lvds@10e10000 {
|
|
compatible = "sirf,atlas7-lvdsc";
|
|
reg = <0x10e10000 0x10000>;
|
|
interrupts = <0 64 0>;
|
|
clocks = <&car 54>;
|
|
resets = <&car 29>;
|
|
};
|
|
|
|
};
|
|
|
|
graphics-iobg {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x12000000 0x12000000 0x1000000>;
|
|
|
|
graphics@12000000 {
|
|
compatible = "powervr,sgx531";
|
|
reg = <0x12000000 0x1000000>;
|
|
interrupts = <0 6 0>;
|
|
clocks = <&car 126>;
|
|
};
|
|
};
|
|
};
|
|
};
|