200 lines
5.8 KiB
C
200 lines
5.8 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/idp.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
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*
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* 2001-09-13: Cliff Brake <cbrake@accelent.com>
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* Initial code
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*
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* 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
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* <http://www.vibren.com> <http://bec-systems.com>
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* Changes for 2.6 kernel.
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*/
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/*
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* Note: this file must be safe to include in assembly files
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*
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* Support for the Vibren PXA255 IDP requires rev04 or later
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* IDP hardware.
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*/
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#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
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#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
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#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS)
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#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000)
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#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000)
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#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000)
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#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000)
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/*
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* virtual memory map
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*/
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#define IDP_COREVOLT_VIRT (0xf0000000)
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#define IDP_COREVOLT_SIZE (1*1024*1024)
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#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
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#define IDP_CPLD_SIZE (1*1024*1024)
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#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
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#error Your custom IO space is getting a bit large !!
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#endif
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#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
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#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
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#ifndef __ASSEMBLY__
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# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x)))
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#else
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# define __CPLD_REG(x) CPLD_P2V(x)
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#endif
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/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
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#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00)
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#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04)
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#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08)
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#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C)
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#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10)
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#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14)
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#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18)
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#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C)
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#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20)
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#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24)
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#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28)
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#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C)
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#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30)
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#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34)
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#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50)
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#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54)
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#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58)
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#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C)
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/* FPGA register virtual addresses */
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#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV)
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#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
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#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL)
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#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
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#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
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#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN)
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#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
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#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
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#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
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#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
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#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
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#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL)
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#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD)
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#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE)
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#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW)
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#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
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#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
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#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS)
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/*
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* Bit masks for various registers
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*/
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// IDP_CPLD_PCCARD_PWR
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#define PCC0_PWR0 (1 << 0)
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#define PCC0_PWR1 (1 << 1)
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#define PCC0_PWR2 (1 << 2)
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#define PCC0_PWR3 (1 << 3)
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#define PCC1_PWR0 (1 << 4)
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#define PCC1_PWR1 (1 << 5)
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#define PCC1_PWR2 (1 << 6)
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#define PCC1_PWR3 (1 << 7)
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// IDP_CPLD_PCCARD_EN
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#define PCC0_RESET (1 << 6)
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#define PCC1_RESET (1 << 7)
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#define PCC0_ENABLE (1 << 0)
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#define PCC1_ENABLE (1 << 1)
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// IDP_CPLD_PCCARDx_STATUS
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#define _PCC_WRPROT (1 << 7) // 7-4 read as low true
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#define _PCC_RESET (1 << 6)
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#define _PCC_IRQ (1 << 5)
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#define _PCC_INPACK (1 << 4)
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#define PCC_BVD2 (1 << 3)
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#define PCC_BVD1 (1 << 2)
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#define PCC_VS2 (1 << 1)
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#define PCC_VS1 (1 << 0)
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#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
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/* A listing of interrupts used by external hardware devices */
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#define TOUCH_PANEL_IRQ IRQ_GPIO(5)
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#define IDE_IRQ IRQ_GPIO(21)
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#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
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#define ETHERNET_IRQ IRQ_GPIO(4)
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#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING
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#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
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#define PCMCIA_S0_CD_VALID IRQ_GPIO(7)
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#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
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#define PCMCIA_S1_CD_VALID IRQ_GPIO(8)
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#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH
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#define PCMCIA_S0_RDYINT IRQ_GPIO(19)
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#define PCMCIA_S1_RDYINT IRQ_GPIO(22)
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/*
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* Macros for LED Driver
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*/
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/* leds 0 = ON */
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#define IDP_HB_LED (1<<5)
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#define IDP_BUSY_LED (1<<6)
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#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED)
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/*
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* macros for MTD driver
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*/
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#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1))
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#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1))
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/*
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* macros for matrix keyboard driver
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*/
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#define KEYBD_MATRIX_NUMBER_INPUTS 7
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#define KEYBD_MATRIX_NUMBER_OUTPUTS 14
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#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE
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#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE
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#define KEYBD_MATRIX_SETTLING_TIME_US 100
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#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2
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#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
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{\
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IDP_CPLD_KB_COL_LOW = outputs;\
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IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
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}
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#define KEYBD_MATRIX_GET_INPUTS(inputs) \
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{\
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inputs = (IDP_CPLD_KB_ROW & 0x7f);\
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}
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