154 lines
5.0 KiB
Plaintext
154 lines
5.0 KiB
Plaintext
KVM Lock Overview
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=================
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1. Acquisition Orders
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---------------------
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(to be written)
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2: Exception
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------------
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Fast page fault:
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Fast page fault is the fast path which fixes the guest page fault out of
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the mmu-lock on x86. Currently, the page fault can be fast only if the
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shadow page table is present and it is caused by write-protect, that means
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we just need change the W bit of the spte.
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What we use to avoid all the race is the SPTE_HOST_WRITEABLE bit and
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SPTE_MMU_WRITEABLE bit on the spte:
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- SPTE_HOST_WRITEABLE means the gfn is writable on host.
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- SPTE_MMU_WRITEABLE means the gfn is writable on mmu. The bit is set when
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the gfn is writable on guest mmu and it is not write-protected by shadow
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page write-protection.
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On fast page fault path, we will use cmpxchg to atomically set the spte W
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bit if spte.SPTE_HOST_WRITEABLE = 1 and spte.SPTE_WRITE_PROTECT = 1, this
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is safe because whenever changing these bits can be detected by cmpxchg.
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But we need carefully check these cases:
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1): The mapping from gfn to pfn
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The mapping from gfn to pfn may be changed since we can only ensure the pfn
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is not changed during cmpxchg. This is a ABA problem, for example, below case
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will happen:
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At the beginning:
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gpte = gfn1
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gfn1 is mapped to pfn1 on host
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spte is the shadow page table entry corresponding with gpte and
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spte = pfn1
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VCPU 0 VCPU0
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on fast page fault path:
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old_spte = *spte;
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pfn1 is swapped out:
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spte = 0;
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pfn1 is re-alloced for gfn2.
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gpte is changed to point to
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gfn2 by the guest:
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spte = pfn1;
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if (cmpxchg(spte, old_spte, old_spte+W)
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mark_page_dirty(vcpu->kvm, gfn1)
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OOPS!!!
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We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap.
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For direct sp, we can easily avoid it since the spte of direct sp is fixed
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to gfn. For indirect sp, before we do cmpxchg, we call gfn_to_pfn_atomic()
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to pin gfn to pfn, because after gfn_to_pfn_atomic():
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- We have held the refcount of pfn that means the pfn can not be freed and
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be reused for another gfn.
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- The pfn is writable that means it can not be shared between different gfns
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by KSM.
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Then, we can ensure the dirty bitmaps is correctly set for a gfn.
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Currently, to simplify the whole things, we disable fast page fault for
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indirect shadow page.
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2): Dirty bit tracking
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In the origin code, the spte can be fast updated (non-atomically) if the
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spte is read-only and the Accessed bit has already been set since the
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Accessed bit and Dirty bit can not be lost.
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But it is not true after fast page fault since the spte can be marked
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writable between reading spte and updating spte. Like below case:
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At the beginning:
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spte.W = 0
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spte.Accessed = 1
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VCPU 0 VCPU0
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In mmu_spte_clear_track_bits():
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old_spte = *spte;
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/* 'if' condition is satisfied. */
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if (old_spte.Accssed == 1 &&
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old_spte.W == 0)
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spte = 0ull;
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on fast page fault path:
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spte.W = 1
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memory write on the spte:
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spte.Dirty = 1
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else
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old_spte = xchg(spte, 0ull)
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if (old_spte.Accssed == 1)
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kvm_set_pfn_accessed(spte.pfn);
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if (old_spte.Dirty == 1)
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kvm_set_pfn_dirty(spte.pfn);
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OOPS!!!
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The Dirty bit is lost in this case.
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In order to avoid this kind of issue, we always treat the spte as "volatile"
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if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
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the spte is always atomicly updated in this case.
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3): flush tlbs due to spte updated
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If the spte is updated from writable to readonly, we should flush all TLBs,
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otherwise rmap_write_protect will find a read-only spte, even though the
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writable spte might be cached on a CPU's TLB.
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As mentioned before, the spte can be updated to writable out of mmu-lock on
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fast page fault path, in order to easily audit the path, we see if TLBs need
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be flushed caused by this reason in mmu_spte_update() since this is a common
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function to update spte (present -> present).
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Since the spte is "volatile" if it can be updated out of mmu-lock, we always
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atomicly update the spte, the race caused by fast page fault can be avoided,
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See the comments in spte_has_volatile_bits() and mmu_spte_update().
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3. Reference
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------------
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Name: kvm_lock
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Type: raw_spinlock
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Arch: any
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Protects: - vm_list
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- hardware virtualization enable/disable
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Comment: 'raw' because hardware enabling/disabling must be atomic /wrt
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migration.
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Name: kvm_arch::tsc_write_lock
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Type: raw_spinlock
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Arch: x86
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Protects: - kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset}
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- tsc offset in vmcb
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Comment: 'raw' because updating the tsc offsets must not be preempted.
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Name: kvm->mmu_lock
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Type: spinlock_t
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Arch: any
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Protects: -shadow page/shadow tlb entry
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Comment: it is a spinlock since it is used in mmu notifier.
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