238 lines
5.3 KiB
C
238 lines
5.3 KiB
C
/*
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* Driver for it913x Frontend
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
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*/
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#ifndef IT913X_FE_H
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#define IT913X_FE_H
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#include <linux/kconfig.h>
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#include <linux/dvb/frontend.h>
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#include "dvb_frontend.h"
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struct ite_config {
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u8 chip_ver;
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u16 chip_type;
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u32 firmware;
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u8 firmware_ver;
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u8 adc_x2;
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u8 tuner_id_0;
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u8 tuner_id_1;
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u8 dual_mode;
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u8 adf;
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/* option to read SIGNAL_LEVEL */
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u8 read_slevel;
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};
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#if IS_ENABLED(CONFIG_DVB_IT913X_FE)
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extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
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u8 i2c_addr, struct ite_config *config);
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#else
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static inline struct dvb_frontend *it913x_fe_attach(
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struct i2c_adapter *i2c_adap,
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u8 i2c_addr, struct ite_config *config)
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{
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printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
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return NULL;
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}
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#endif /* CONFIG_IT913X_FE */
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#define I2C_BASE_ADDR 0x10
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#define DEV_0 0x0
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#define DEV_1 0x10
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#define PRO_LINK 0x0
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#define PRO_DMOD 0x1
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#define DEV_0_DMOD (PRO_DMOD << 0x7)
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#define DEV_1_DMOD (DEV_0_DMOD | DEV_1)
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#define CHIP2_I2C_ADDR 0x3a
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#define AFE_MEM0 0xfb24
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#define MP2_SW_RST 0xf99d
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#define MP2IF2_SW_RST 0xf9a4
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#define PADODPU 0xd827
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#define THIRDODPU 0xd828
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#define AGC_O_D 0xd829
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#define EP0_TX_EN 0xdd11
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#define EP0_TX_NAK 0xdd13
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#define EP4_TX_LEN_LSB 0xdd88
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#define EP4_TX_LEN_MSB 0xdd89
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#define EP4_MAX_PKT 0xdd0c
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#define EP5_TX_LEN_LSB 0xdd8a
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#define EP5_TX_LEN_MSB 0xdd8b
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#define EP5_MAX_PKT 0xdd0d
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#define IO_MUX_POWER_CLK 0xd800
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#define CLK_O_EN 0xd81a
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#define I2C_CLK 0xf103
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#define I2C_CLK_100 0x7
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#define I2C_CLK_400 0x1a
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#define D_TPSD_LOCK 0xf5a9
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#define MP2IF2_EN 0xf9a3
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#define MP2IF_SERIAL 0xf985
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#define TSIS_ENABLE 0xf9cd
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#define MP2IF2_HALF_PSB 0xf9a5
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#define MP2IF_STOP_EN 0xf9b5
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#define MPEG_FULL_SPEED 0xf990
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#define TOP_HOSTB_SER_MODE 0xd91c
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#define PID_RST 0xf992
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#define PID_EN 0xf993
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#define PID_INX_EN 0xf994
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#define PID_INX 0xf995
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#define PID_LSB 0xf996
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#define PID_MSB 0xf997
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#define MP2IF_MPEG_PAR_MODE 0xf986
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#define DCA_UPPER_CHIP 0xf731
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#define DCA_LOWER_CHIP 0xf732
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#define DCA_PLATCH 0xf730
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#define DCA_FPGA_LATCH 0xf778
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#define DCA_STAND_ALONE 0xf73c
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#define DCA_ENABLE 0xf776
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#define DVBT_INTEN 0xf41f
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#define DVBT_ENABLE 0xf41a
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#define HOSTB_DCA_LOWER 0xd91f
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#define HOSTB_MPEG_PAR_MODE 0xd91b
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#define HOSTB_MPEG_SER_MODE 0xd91c
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#define HOSTB_MPEG_SER_DO7 0xd91d
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#define HOSTB_DCA_UPPER 0xd91e
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#define PADMISCDR2 0xd830
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#define PADMISCDR4 0xd831
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#define PADMISCDR8 0xd832
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#define PADMISCDRSR 0xd833
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#define LOCK3_OUT 0xd8fd
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#define GPIOH1_O 0xd8af
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#define GPIOH1_EN 0xd8b0
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#define GPIOH1_ON 0xd8b1
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#define GPIOH3_O 0xd8b3
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#define GPIOH3_EN 0xd8b4
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#define GPIOH3_ON 0xd8b5
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#define GPIOH5_O 0xd8bb
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#define GPIOH5_EN 0xd8bc
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#define GPIOH5_ON 0xd8bd
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#define AFE_MEM0 0xfb24
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#define REG_TPSD_TX_MODE 0xf900
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#define REG_TPSD_GI 0xf901
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#define REG_TPSD_HIER 0xf902
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#define REG_TPSD_CONST 0xf903
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#define REG_BW 0xf904
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#define REG_PRIV 0xf905
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#define REG_TPSD_HP_CODE 0xf906
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#define REG_TPSD_LP_CODE 0xf907
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#define MP2IF_SYNC_LK 0xf999
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#define ADC_FREQ 0xf1cd
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#define TRIGGER_OFSM 0x0000
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/* COEFF Registers start at 0x0001 to 0x0020 */
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#define COEFF_1_2048 0x0001
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#define XTAL_CLK 0x0025
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#define BFS_FCW 0x0029
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/* Error Regs */
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#define RSD_ABORT_PKT_LSB 0x0032
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#define RSD_ABORT_PKT_MSB 0x0033
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#define RSD_BIT_ERR_0_7 0x0034
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#define RSD_BIT_ERR_8_15 0x0035
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#define RSD_BIT_ERR_23_16 0x0036
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#define RSD_BIT_COUNT_LSB 0x0037
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#define RSD_BIT_COUNT_MSB 0x0038
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#define TPSD_LOCK 0x003c
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#define TRAINING_MODE 0x0040
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#define ADC_X_2 0x0045
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#define TUNER_ID 0x0046
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#define EMPTY_CHANNEL_STATUS 0x0047
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#define SIGNAL_LEVEL 0x0048
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#define SIGNAL_QUALITY 0x0049
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#define EST_SIGNAL_LEVEL 0x004a
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#define FREE_BAND 0x004b
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#define SUSPEND_FLAG 0x004c
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#define VAR_P_INBAND 0x00f7
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/* Build in tuner types */
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#define IT9137 0x38
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#define IT9135_38 0x38
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#define IT9135_51 0x51
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#define IT9135_52 0x52
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#define IT9135_60 0x60
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#define IT9135_61 0x61
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#define IT9135_62 0x62
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enum {
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CMD_DEMOD_READ = 0,
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CMD_DEMOD_WRITE,
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CMD_TUNER_READ,
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CMD_TUNER_WRITE,
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CMD_REG_EEPROM_READ,
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CMD_REG_EEPROM_WRITE,
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CMD_DATA_READ,
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CMD_VAR_READ = 8,
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CMD_VAR_WRITE,
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CMD_PLATFORM_GET,
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CMD_PLATFORM_SET,
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CMD_IP_CACHE,
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CMD_IP_ADD,
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CMD_IP_REMOVE,
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CMD_PID_ADD,
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CMD_PID_REMOVE,
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CMD_SIPSI_GET,
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CMD_SIPSI_MPE_RESET,
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CMD_H_PID_ADD = 0x15,
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CMD_H_PID_REMOVE,
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CMD_ABORT,
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CMD_IR_GET,
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CMD_IR_SET,
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CMD_FW_DOWNLOAD = 0x21,
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CMD_QUERYINFO,
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CMD_BOOT,
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CMD_FW_DOWNLOAD_BEGIN,
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CMD_FW_DOWNLOAD_END,
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CMD_RUN_CODE,
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CMD_SCATTER_READ = 0x28,
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CMD_SCATTER_WRITE,
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CMD_GENERIC_READ,
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CMD_GENERIC_WRITE
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};
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enum {
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READ_LONG,
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WRITE_LONG,
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READ_SHORT,
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WRITE_SHORT,
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READ_DATA,
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WRITE_DATA,
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WRITE_CMD,
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};
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enum {
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IT9135_AUTO = 0,
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IT9137_FW,
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IT9135_V1_FW,
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IT9135_V2_FW,
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};
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#endif /* IT913X_FE_H */
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