558 lines
11 KiB
C
558 lines
11 KiB
C
/*
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* arch/arm/mach-spear3xx/spear3xx.c
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*
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* SPEAr3XX machines common source file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/types.h>
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#include <linux/amba/pl061.h>
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#include <linux/ptrace.h>
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#include <linux/io.h>
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#include <asm/hardware/vic.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <mach/generic.h>
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#include <mach/hardware.h>
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/* Add spear3xx machines common devices here */
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/* gpio device registration */
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static struct pl061_platform_data gpio_plat_data = {
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.gpio_base = 0,
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.irq_base = SPEAR_GPIO_INT_BASE,
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};
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struct amba_device gpio_device = {
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.dev = {
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.init_name = "gpio",
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.platform_data = &gpio_plat_data,
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},
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.res = {
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.start = SPEAR3XX_ICM3_GPIO_BASE,
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.end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = {IRQ_BASIC_GPIO, NO_IRQ},
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};
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/* uart device registration */
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struct amba_device uart_device = {
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.dev = {
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.init_name = "uart",
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},
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.res = {
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.start = SPEAR3XX_ICM1_UART_BASE,
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.end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = {IRQ_UART, NO_IRQ},
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};
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/* Do spear3xx familiy common initialization part here */
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void __init spear3xx_init(void)
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{
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/* nothing to do for now */
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}
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/* This will initialize vic */
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void __init spear3xx_init_irq(void)
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{
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vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
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}
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/* Following will create static virtual/physical mappings */
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struct map_desc spear3xx_io_desc[] __initdata = {
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{
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.virtual = VA_SPEAR3XX_ICM1_UART_BASE,
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.pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = VA_SPEAR3XX_ML1_VIC_BASE,
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.pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
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.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
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.pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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},
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};
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/* This will create static memory mapping for selected devices */
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void __init spear3xx_map_io(void)
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{
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iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
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/* This will initialize clock framework */
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clk_init();
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}
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/* pad multiplexing support */
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/* devices */
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struct pmx_dev_mode pmx_firda_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_FIRDA_MASK,
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},
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};
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struct pmx_dev pmx_firda = {
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.name = "firda",
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.modes = pmx_firda_modes,
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.mode_count = ARRAY_SIZE(pmx_firda_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_i2c_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_I2C_MASK,
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},
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};
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struct pmx_dev pmx_i2c = {
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.name = "i2c",
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.modes = pmx_i2c_modes,
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.mode_count = ARRAY_SIZE(pmx_i2c_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_ssp_cs_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_SSP_CS_MASK,
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},
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};
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struct pmx_dev pmx_ssp_cs = {
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.name = "ssp_chip_selects",
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.modes = pmx_ssp_cs_modes,
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.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_ssp_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_SSP_MASK,
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},
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};
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struct pmx_dev pmx_ssp = {
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.name = "ssp",
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.modes = pmx_ssp_modes,
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.mode_count = ARRAY_SIZE(pmx_ssp_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_mii_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev pmx_mii = {
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.name = "mii",
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.modes = pmx_mii_modes,
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.mode_count = ARRAY_SIZE(pmx_mii_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_GPIO_PIN0_MASK,
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},
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};
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struct pmx_dev pmx_gpio_pin0 = {
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.name = "gpio_pin0",
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.modes = pmx_gpio_pin0_modes,
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.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_GPIO_PIN1_MASK,
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},
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};
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struct pmx_dev pmx_gpio_pin1 = {
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.name = "gpio_pin1",
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.modes = pmx_gpio_pin1_modes,
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.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_GPIO_PIN2_MASK,
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},
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};
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struct pmx_dev pmx_gpio_pin2 = {
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.name = "gpio_pin2",
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.modes = pmx_gpio_pin2_modes,
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.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_GPIO_PIN3_MASK,
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},
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};
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struct pmx_dev pmx_gpio_pin3 = {
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.name = "gpio_pin3",
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.modes = pmx_gpio_pin3_modes,
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.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_GPIO_PIN4_MASK,
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},
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};
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struct pmx_dev pmx_gpio_pin4 = {
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.name = "gpio_pin4",
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.modes = pmx_gpio_pin4_modes,
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.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_GPIO_PIN5_MASK,
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},
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};
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struct pmx_dev pmx_gpio_pin5 = {
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.name = "gpio_pin5",
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.modes = pmx_gpio_pin5_modes,
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.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_uart0_modem_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_UART0_MODEM_MASK,
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},
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};
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struct pmx_dev pmx_uart0_modem = {
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.name = "uart0_modem",
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.modes = pmx_uart0_modem_modes,
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.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_uart0_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_UART0_MASK,
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},
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};
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struct pmx_dev pmx_uart0 = {
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.name = "uart0",
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.modes = pmx_uart0_modes,
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.mode_count = ARRAY_SIZE(pmx_uart0_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_timer_3_4_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_TIMER_3_4_MASK,
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},
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};
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struct pmx_dev pmx_timer_3_4 = {
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.name = "timer_3_4",
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.modes = pmx_timer_3_4_modes,
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.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
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.enb_on_reset = 0,
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};
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struct pmx_dev_mode pmx_timer_1_2_modes[] = {
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{
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.ids = 0xffffffff,
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.mask = PMX_TIMER_1_2_MASK,
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},
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};
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struct pmx_dev pmx_timer_1_2 = {
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.name = "timer_1_2",
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.modes = pmx_timer_1_2_modes,
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.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
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.enb_on_reset = 0,
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};
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#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
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/* plgpios devices */
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struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_FIRDA_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_0_1 = {
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.name = "plgpio 0 and 1",
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.modes = pmx_plgpio_0_1_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_UART0_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_2_3 = {
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.name = "plgpio 2 and 3",
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.modes = pmx_plgpio_2_3_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_I2C_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_4_5 = {
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.name = "plgpio 4 and 5",
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.modes = pmx_plgpio_4_5_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_SSP_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_6_9 = {
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.name = "plgpio 6 to 9",
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.modes = pmx_plgpio_6_9_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_MII_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_10_27 = {
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.name = "plgpio 10 to 27",
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.modes = pmx_plgpio_10_27_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_28_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_GPIO_PIN0_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_28 = {
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.name = "plgpio 28",
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.modes = pmx_plgpio_28_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_29_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_GPIO_PIN1_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_29 = {
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.name = "plgpio 29",
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.modes = pmx_plgpio_29_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_30_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_GPIO_PIN2_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_30 = {
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.name = "plgpio 30",
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.modes = pmx_plgpio_30_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_31_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_GPIO_PIN3_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_31 = {
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.name = "plgpio 31",
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.modes = pmx_plgpio_31_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_32_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_GPIO_PIN4_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_32 = {
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.name = "plgpio 32",
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.modes = pmx_plgpio_32_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_33_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_GPIO_PIN5_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_33 = {
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.name = "plgpio 33",
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.modes = pmx_plgpio_33_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_SSP_CS_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_34_36 = {
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.name = "plgpio 34 to 36",
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.modes = pmx_plgpio_34_36_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_UART0_MODEM_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_37_42 = {
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.name = "plgpio 37 to 42",
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.modes = pmx_plgpio_37_42_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_TIMER_1_2_MASK,
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},
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};
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struct pmx_dev pmx_plgpio_43_44_47_48 = {
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.name = "plgpio 43, 44, 47 and 48",
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.modes = pmx_plgpio_43_44_47_48_modes,
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.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
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.enb_on_reset = 1,
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};
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struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
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{
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.ids = 0x00,
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.mask = PMX_TIMER_3_4_MASK,
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},
|
|
};
|
|
|
|
struct pmx_dev pmx_plgpio_45_46_49_50 = {
|
|
.name = "plgpio 45, 46, 49 and 50",
|
|
.modes = pmx_plgpio_45_46_49_50_modes,
|
|
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
|
|
.enb_on_reset = 1,
|
|
};
|
|
#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
|
|
|
|
static void __init spear3xx_timer_init(void)
|
|
{
|
|
char pclk_name[] = "pll3_48m_clk";
|
|
struct clk *gpt_clk, *pclk;
|
|
|
|
/* get the system timer clock */
|
|
gpt_clk = clk_get_sys("gpt0", NULL);
|
|
if (IS_ERR(gpt_clk)) {
|
|
pr_err("%s:couldn't get clk for gpt\n", __func__);
|
|
BUG();
|
|
}
|
|
|
|
/* get the suitable parent clock for timer*/
|
|
pclk = clk_get(NULL, pclk_name);
|
|
if (IS_ERR(pclk)) {
|
|
pr_err("%s:couldn't get %s as parent for gpt\n",
|
|
__func__, pclk_name);
|
|
BUG();
|
|
}
|
|
|
|
clk_set_parent(gpt_clk, pclk);
|
|
clk_put(gpt_clk);
|
|
clk_put(pclk);
|
|
|
|
spear_setup_timer();
|
|
}
|
|
|
|
struct sys_timer spear3xx_timer = {
|
|
.init = spear3xx_timer_init,
|
|
};
|