131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P6440 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <mach/map.h>
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#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
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#define S5P_APLL_LOCK S5P_CLKREG(0x00)
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#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
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#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
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#define S5P_APLL_CON S5P_CLKREG(0x0C)
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#define S5P_MPLL_CON S5P_CLKREG(0x10)
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#define S5P_EPLL_CON S5P_CLKREG(0x14)
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#define S5P_EPLL_CON_K S5P_CLKREG(0x18)
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#define S5P_CLK_SRC0 S5P_CLKREG(0x1C)
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#define S5P_CLK_DIV0 S5P_CLKREG(0x20)
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#define S5P_CLK_DIV1 S5P_CLKREG(0x24)
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#define S5P_CLK_DIV2 S5P_CLKREG(0x28)
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#define S5P_CLK_OUT S5P_CLKREG(0x2C)
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#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
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#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34)
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#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
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#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
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#define S5P_CLK_DIV3 S5P_CLKREG(0x40)
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#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
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#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
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#define S5P_AHB_CON0 S5P_CLKREG(0x100)
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#define S5P_CLK_SRC1 S5P_CLKREG(0x10C)
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#define S5P_SWRESET S5P_CLKREG(0x114)
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#define S5P_SYS_ID S5P_CLKREG(0x118)
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#define S5P_SYS_OTHERS S5P_CLKREG(0x11C)
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#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C)
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#define S5P_PWR_CFG S5P_CLKREG(0x804)
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#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
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#define S5P_NORMAL_CFG S5P_CLKREG(0x810)
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#define S5P_STOP_CFG S5P_CLKREG(0x814)
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#define S5P_SLEEP_CFG S5P_CLKREG(0x818)
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#define S5P_OSC_FREQ S5P_CLKREG(0x820)
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#define S5P_OSC_STABLE S5P_CLKREG(0x824)
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#define S5P_PWR_STABLE S5P_CLKREG(0x828)
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#define S5P_MTC_STABLE S5P_CLKREG(0x830)
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#define S5P_OTHERS S5P_CLKREG(0x900)
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#define S5P_RST_STAT S5P_CLKREG(0x904)
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#define S5P_WAKEUP_STAT S5P_CLKREG(0x908)
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#define S5P_SLPEN S5P_CLKREG(0x930)
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#define S5P_INFORM0 S5P_CLKREG(0xA00)
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#define S5P_INFORM1 S5P_CLKREG(0xA04)
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#define S5P_INFORM2 S5P_CLKREG(0xA08)
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#define S5P_INFORM3 S5P_CLKREG(0xA0C)
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/* CLKDIV0 */
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#define S5P_CLKDIV0_PCLK_MASK (0xf << 12)
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#define S5P_CLKDIV0_PCLK_SHIFT (12)
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#define S5P_CLKDIV0_HCLK_MASK (0xf << 8)
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#define S5P_CLKDIV0_HCLK_SHIFT (8)
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#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4)
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#define S5P_CLKDIV0_ARM_MASK (0xf << 0)
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#define S5P_CLKDIV0_ARM_SHIFT (0)
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/* CLKDIV3 */
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#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12)
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#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12)
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#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8)
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#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8)
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/* HCLK0 GATE Registers */
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#define S5P_CLKCON_HCLK0_USB (1<<20)
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#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19)
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#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18)
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#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17)
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#define S5P_CLKCON_HCLK0_POST0 (1<<5)
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/* HCLK1 GATE Registers */
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#define S5P_CLKCON_HCLK1_DISPCON (1<<1)
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/* PCLK GATE Registers */
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#define S5P_CLKCON_PCLK_IIS2 (1<<26)
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#define S5P_CLKCON_PCLK_SPI1 (1<<22)
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#define S5P_CLKCON_PCLK_SPI0 (1<<21)
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#define S5P_CLKCON_PCLK_GPIO (1<<18)
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#define S5P_CLKCON_PCLK_IIC0 (1<<17)
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#define S5P_CLKCON_PCLK_TSADC (1<<12)
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#define S5P_CLKCON_PCLK_PWM (1<<7)
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#define S5P_CLKCON_PCLK_RTC (1<<6)
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#define S5P_CLKCON_PCLK_WDT (1<<5)
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#define S5P_CLKCON_PCLK_UART3 (1<<4)
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#define S5P_CLKCON_PCLK_UART2 (1<<3)
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#define S5P_CLKCON_PCLK_UART1 (1<<2)
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#define S5P_CLKCON_PCLK_UART0 (1<<1)
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/* SCLK0 GATE Registers */
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#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29)
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#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28)
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#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27)
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#define S5P_CLKCON_SCLK0_MMC2 (1<<26)
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#define S5P_CLKCON_SCLK0_MMC1 (1<<25)
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#define S5P_CLKCON_SCLK0_MMC0 (1<<24)
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#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23)
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#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22)
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#define S5P_CLKCON_SCLK0_SPI1 (1<<21)
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#define S5P_CLKCON_SCLK0_SPI0 (1<<20)
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#define S5P_CLKCON_SCLK0_UART (1<<5)
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/* SCLK1 GATE Registers */
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/* MEM0 GATE Registers */
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#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2)
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/*OTHERS Resgister */
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#define S5P_OTHERS_USB_SIG_MASK (1<<16)
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#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6)
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/* Compatibility defines */
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#define ARM_CLK_DIV S5P_CLK_DIV0
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#define ARM_DIV_RATIO_SHIFT 0
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#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT)
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#endif /* __ASM_ARCH_REGS_CLOCK_H */
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