268 lines
6.2 KiB
C
268 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_vbif.h"
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#define VBIF_VERSION 0x0000
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#define VBIF_CLK_FORCE_CTRL0 0x0008
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#define VBIF_CLK_FORCE_CTRL1 0x000C
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#define VBIF_QOS_REMAP_00 0x0020
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#define VBIF_QOS_REMAP_01 0x0024
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#define VBIF_QOS_REMAP_10 0x0028
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#define VBIF_QOS_REMAP_11 0x002C
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#define VBIF_WRITE_GATHER_EN 0x00AC
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#define VBIF_IN_RD_LIM_CONF0 0x00B0
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#define VBIF_IN_RD_LIM_CONF1 0x00B4
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#define VBIF_IN_RD_LIM_CONF2 0x00B8
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#define VBIF_IN_WR_LIM_CONF0 0x00C0
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#define VBIF_IN_WR_LIM_CONF1 0x00C4
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#define VBIF_IN_WR_LIM_CONF2 0x00C8
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#define VBIF_OUT_RD_LIM_CONF0 0x00D0
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#define VBIF_OUT_WR_LIM_CONF0 0x00D4
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#define VBIF_OUT_AXI_AMEMTYPE_CONF0 0x0160
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#define VBIF_OUT_AXI_AMEMTYPE_CONF1 0x0164
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#define VBIF_XIN_PND_ERR 0x0190
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#define VBIF_XIN_SRC_ERR 0x0194
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#define VBIF_XIN_CLR_ERR 0x019C
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#define VBIF_XIN_HALT_CTRL0 0x0200
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#define VBIF_XIN_HALT_CTRL1 0x0204
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#define VBIF_XINL_QOS_RP_REMAP_000 0x0550
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#define VBIF_XINL_QOS_LVL_REMAP_000(v) (v < DPU_HW_VER_400 ? 0x570 : 0x0590)
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static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif,
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u32 *pnd_errors, u32 *src_errors)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 pnd, src;
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if (!vbif)
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return;
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c = &vbif->hw;
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pnd = DPU_REG_READ(c, VBIF_XIN_PND_ERR);
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src = DPU_REG_READ(c, VBIF_XIN_SRC_ERR);
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if (pnd_errors)
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*pnd_errors = pnd;
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if (src_errors)
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*src_errors = src;
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DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src);
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}
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static void dpu_hw_set_mem_type(struct dpu_hw_vbif *vbif,
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u32 xin_id, u32 value)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 reg_off;
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u32 bit_off;
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u32 reg_val;
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/*
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* Assume 4 bits per bit field, 8 fields per 32-bit register so
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* 16 bit fields maximum across two registers
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*/
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if (!vbif || xin_id >= MAX_XIN_COUNT || xin_id >= 16)
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return;
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c = &vbif->hw;
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if (xin_id >= 8) {
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xin_id -= 8;
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reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1;
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} else {
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reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0;
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}
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bit_off = (xin_id & 0x7) * 4;
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reg_val = DPU_REG_READ(c, reg_off);
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reg_val &= ~(0x7 << bit_off);
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reg_val |= (value & 0x7) << bit_off;
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DPU_REG_WRITE(c, reg_off, reg_val);
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}
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static void dpu_hw_set_limit_conf(struct dpu_hw_vbif *vbif,
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u32 xin_id, bool rd, u32 limit)
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{
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struct dpu_hw_blk_reg_map *c = &vbif->hw;
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u32 reg_val;
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u32 reg_off;
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u32 bit_off;
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if (rd)
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reg_off = VBIF_IN_RD_LIM_CONF0;
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else
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reg_off = VBIF_IN_WR_LIM_CONF0;
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reg_off += (xin_id / 4) * 4;
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bit_off = (xin_id % 4) * 8;
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reg_val = DPU_REG_READ(c, reg_off);
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reg_val &= ~(0xFF << bit_off);
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reg_val |= (limit) << bit_off;
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DPU_REG_WRITE(c, reg_off, reg_val);
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}
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static u32 dpu_hw_get_limit_conf(struct dpu_hw_vbif *vbif,
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u32 xin_id, bool rd)
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{
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struct dpu_hw_blk_reg_map *c = &vbif->hw;
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u32 reg_val;
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u32 reg_off;
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u32 bit_off;
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u32 limit;
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if (rd)
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reg_off = VBIF_IN_RD_LIM_CONF0;
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else
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reg_off = VBIF_IN_WR_LIM_CONF0;
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reg_off += (xin_id / 4) * 4;
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bit_off = (xin_id % 4) * 8;
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reg_val = DPU_REG_READ(c, reg_off);
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limit = (reg_val >> bit_off) & 0xFF;
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return limit;
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}
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static void dpu_hw_set_halt_ctrl(struct dpu_hw_vbif *vbif,
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u32 xin_id, bool enable)
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{
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struct dpu_hw_blk_reg_map *c = &vbif->hw;
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u32 reg_val;
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reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0);
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if (enable)
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reg_val |= BIT(xin_id);
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else
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reg_val &= ~BIT(xin_id);
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DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val);
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}
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static bool dpu_hw_get_halt_ctrl(struct dpu_hw_vbif *vbif,
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u32 xin_id)
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{
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struct dpu_hw_blk_reg_map *c = &vbif->hw;
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u32 reg_val;
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reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1);
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return (reg_val & BIT(xin_id)) ? true : false;
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}
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static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
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u32 xin_id, u32 level, u32 remap_level)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift;
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if (!vbif)
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return;
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c = &vbif->hw;
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reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion);
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reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);
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reg_shift = (xin_id & 0x7) * 4;
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reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);
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reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high);
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mask = 0x7 << reg_shift;
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reg_val &= ~mask;
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reg_val |= (remap_level << reg_shift) & mask;
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reg_val_lvl &= ~mask;
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reg_val_lvl |= (remap_level << reg_shift) & mask;
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DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);
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DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl);
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}
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static void dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 reg_val;
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if (!vbif || xin_id >= MAX_XIN_COUNT)
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return;
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c = &vbif->hw;
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reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN);
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reg_val |= BIT(xin_id);
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DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val);
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}
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static void _setup_vbif_ops(struct dpu_hw_vbif_ops *ops,
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unsigned long cap)
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{
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ops->set_limit_conf = dpu_hw_set_limit_conf;
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ops->get_limit_conf = dpu_hw_get_limit_conf;
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ops->set_halt_ctrl = dpu_hw_set_halt_ctrl;
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ops->get_halt_ctrl = dpu_hw_get_halt_ctrl;
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if (test_bit(DPU_VBIF_QOS_REMAP, &cap))
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ops->set_qos_remap = dpu_hw_set_qos_remap;
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ops->set_mem_type = dpu_hw_set_mem_type;
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ops->clear_errors = dpu_hw_clear_errors;
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ops->set_write_gather_en = dpu_hw_set_write_gather_en;
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}
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static const struct dpu_vbif_cfg *_top_offset(enum dpu_vbif vbif,
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const struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->vbif_count; i++) {
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if (vbif == m->vbif[i].id) {
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b->base_off = addr;
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b->blk_off = m->vbif[i].base;
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b->length = m->vbif[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_VBIF;
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return &m->vbif[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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struct dpu_hw_vbif *dpu_hw_vbif_init(enum dpu_vbif idx,
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void __iomem *addr,
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const struct dpu_mdss_cfg *m)
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{
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struct dpu_hw_vbif *c;
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const struct dpu_vbif_cfg *cfg;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _top_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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/*
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* Assign ops
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*/
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c->idx = idx;
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c->cap = cfg;
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_setup_vbif_ops(&c->ops, c->cap->features);
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/* no need to register sub-range in dpu dbg, dump entire vbif io base */
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return c;
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}
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void dpu_hw_vbif_destroy(struct dpu_hw_vbif *vbif)
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{
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kfree(vbif);
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}
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