292 lines
7.2 KiB
C
292 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/iopoll.h>
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#include "dpu_hw_mdss.h"
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_pingpong.h"
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#include "dpu_kms.h"
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#include "dpu_trace.h"
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#define PP_TEAR_CHECK_EN 0x000
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#define PP_SYNC_CONFIG_VSYNC 0x004
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#define PP_SYNC_CONFIG_HEIGHT 0x008
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#define PP_SYNC_WRCOUNT 0x00C
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#define PP_VSYNC_INIT_VAL 0x010
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#define PP_INT_COUNT_VAL 0x014
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#define PP_SYNC_THRESH 0x018
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#define PP_START_POS 0x01C
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#define PP_RD_PTR_IRQ 0x020
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#define PP_WR_PTR_IRQ 0x024
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#define PP_OUT_LINE_COUNT 0x028
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#define PP_LINE_COUNT 0x02C
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#define PP_AUTOREFRESH_CONFIG 0x030
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#define PP_FBC_MODE 0x034
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#define PP_FBC_BUDGET_CTL 0x038
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#define PP_FBC_LOSSY_MODE 0x03C
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#define PP_DITHER_EN 0x000
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#define PP_DITHER_BITDEPTH 0x004
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#define PP_DITHER_MATRIX 0x008
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#define DITHER_DEPTH_MAP_INDEX 9
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static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
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0, 0, 0, 0, 0, 0, 0, 1, 2
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};
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static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
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const struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->pingpong_count; i++) {
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if (pp == m->pingpong[i].id) {
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b->base_off = addr;
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b->blk_off = m->pingpong[i].base;
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b->length = m->pingpong[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_PINGPONG;
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return &m->pingpong[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp,
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struct dpu_hw_dither_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 i, base, data = 0;
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c = &pp->hw;
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base = pp->caps->sblk->dither.base;
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if (!cfg) {
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DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);
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return;
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}
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data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2);
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data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2;
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data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4;
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data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6;
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data |= (cfg->temporal_en) ? (1 << 8) : 0;
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DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);
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for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) {
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data = (cfg->matrix[i] & REG_MASK(4)) |
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((cfg->matrix[i + 1] & REG_MASK(4)) << 4) |
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((cfg->matrix[i + 2] & REG_MASK(4)) << 8) |
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((cfg->matrix[i + 3] & REG_MASK(4)) << 12);
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DPU_REG_WRITE(c, base + PP_DITHER_MATRIX + i, data);
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}
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DPU_REG_WRITE(c, base + PP_DITHER_EN, 1);
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}
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static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp,
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struct dpu_hw_tear_check *te)
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{
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struct dpu_hw_blk_reg_map *c;
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int cfg;
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if (!pp || !te)
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return -EINVAL;
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c = &pp->hw;
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cfg = BIT(19); /*VSYNC_COUNTER_EN */
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if (te->hw_vsync_mode)
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cfg |= BIT(20);
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cfg |= te->vsync_count;
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DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
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DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
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DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);
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DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);
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DPU_REG_WRITE(c, PP_START_POS, te->start_pos);
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DPU_REG_WRITE(c, PP_SYNC_THRESH,
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((te->sync_threshold_continue << 16) |
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te->sync_threshold_start));
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DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,
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(te->start_pos + te->sync_threshold_start + 1));
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return 0;
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}
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static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp,
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u32 frame_count, bool enable)
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{
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DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG,
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enable ? (BIT(31) | frame_count) : 0);
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}
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/*
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* dpu_hw_pp_get_autorefresh_config - Get autorefresh config from HW
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* @pp: DPU pingpong structure
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* @frame_count: Used to return the current frame count from hw
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*
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* Returns: True if autorefresh enabled, false if disabled.
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*/
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static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp,
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u32 *frame_count)
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{
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u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG);
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if (frame_count != NULL)
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*frame_count = val & 0xffff;
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return !!((val & BIT(31)) >> 31);
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}
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static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
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u32 timeout_us)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 val;
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int rc;
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if (!pp)
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return -EINVAL;
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c = &pp->hw;
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rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT,
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val, (val & 0xffff) >= 1, 10, timeout_us);
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return rc;
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}
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static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable)
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{
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struct dpu_hw_blk_reg_map *c;
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if (!pp)
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return -EINVAL;
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c = &pp->hw;
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DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable);
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return 0;
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}
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static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp,
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bool enable_external_te)
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{
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struct dpu_hw_blk_reg_map *c = &pp->hw;
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u32 cfg;
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int orig;
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if (!pp)
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return -EINVAL;
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c = &pp->hw;
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cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);
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orig = (bool)(cfg & BIT(20));
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if (enable_external_te)
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cfg |= BIT(20);
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else
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cfg &= ~BIT(20);
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DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
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trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
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return orig;
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}
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static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp,
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struct dpu_hw_pp_vsync_info *info)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 val;
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if (!pp || !info)
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return -EINVAL;
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c = &pp->hw;
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val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);
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info->rd_ptr_init_val = val & 0xffff;
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val = DPU_REG_READ(c, PP_INT_COUNT_VAL);
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info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
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info->rd_ptr_line_count = val & 0xffff;
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val = DPU_REG_READ(c, PP_LINE_COUNT);
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info->wr_ptr_line_count = val & 0xffff;
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return 0;
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}
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static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
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{
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struct dpu_hw_blk_reg_map *c = &pp->hw;
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u32 height, init;
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u32 line = 0xFFFF;
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if (!pp)
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return 0;
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c = &pp->hw;
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init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;
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height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;
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if (height < init)
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return line;
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line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;
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if (line < init)
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line += (0xFFFF - init);
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else
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line -= init;
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return line;
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}
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static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
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unsigned long features)
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{
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c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config;
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c->ops.enable_tearcheck = dpu_hw_pp_enable_te;
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c->ops.connect_external_te = dpu_hw_pp_connect_external_te;
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c->ops.get_vsync_info = dpu_hw_pp_get_vsync_info;
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c->ops.setup_autorefresh = dpu_hw_pp_setup_autorefresh_config;
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c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config;
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c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
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c->ops.get_line_count = dpu_hw_pp_get_line_count;
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if (test_bit(DPU_PINGPONG_DITHER, &features))
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c->ops.setup_dither = dpu_hw_pp_setup_dither;
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};
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struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
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void __iomem *addr,
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const struct dpu_mdss_cfg *m)
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{
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struct dpu_hw_pingpong *c;
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const struct dpu_pingpong_cfg *cfg;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _pingpong_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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c->idx = idx;
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c->caps = cfg;
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_setup_pingpong_ops(c, c->caps->features);
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return c;
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}
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void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
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{
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kfree(pp);
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}
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