232 lines
6.2 KiB
C
232 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_CTL_H
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#define _DPU_HW_CTL_H
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_sspp.h"
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#include "dpu_hw_blk.h"
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/**
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* dpu_ctl_mode_sel: Interface mode selection
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* DPU_CTL_MODE_SEL_VID: Video mode interface
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* DPU_CTL_MODE_SEL_CMD: Command mode interface
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*/
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enum dpu_ctl_mode_sel {
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DPU_CTL_MODE_SEL_VID = 0,
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DPU_CTL_MODE_SEL_CMD
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};
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struct dpu_hw_ctl;
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/**
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* struct dpu_hw_stage_cfg - blending stage cfg
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* @stage : SSPP_ID at each stage
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* @multirect_index: index of the rectangle of SSPP.
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*/
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struct dpu_hw_stage_cfg {
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enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
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enum dpu_sspp_multirect_index multirect_index
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[DPU_STAGE_MAX][PIPES_PER_STAGE];
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};
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/**
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* struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
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* @intf : Interface id
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* @mode_3d: 3d mux configuration
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* @merge_3d: 3d merge block used
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* @intf_mode_sel: Interface mode, cmd / vid
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* @stream_sel: Stream selection for multi-stream interfaces
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*/
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struct dpu_hw_intf_cfg {
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enum dpu_intf intf;
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enum dpu_3d_blend_mode mode_3d;
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enum dpu_merge_3d merge_3d;
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enum dpu_ctl_mode_sel intf_mode_sel;
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int stream_sel;
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};
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/**
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* struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct dpu_hw_ctl_ops {
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/**
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* kickoff hw operation for Sw controlled interfaces
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* DSI cmd mode and WB interface are SW controlled
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* @ctx : ctl path ctx pointer
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*/
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void (*trigger_start)(struct dpu_hw_ctl *ctx);
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/**
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* kickoff prepare is in progress hw operation for sw
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* controlled interfaces: DSI cmd mode and WB interface
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* are SW controlled
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* @ctx : ctl path ctx pointer
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*/
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void (*trigger_pending)(struct dpu_hw_ctl *ctx);
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/**
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* Clear the value of the cached pending_flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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*/
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void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);
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/**
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* Query the value of the cached pending_flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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*/
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u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx);
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/**
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* OR in the given flushbits to the cached pending_flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @flushbits : module flushmask
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*/
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void (*update_pending_flush)(struct dpu_hw_ctl *ctx,
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u32 flushbits);
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/**
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* OR in the given flushbits to the cached pending_(intf_)flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : interface block index
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*/
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void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx,
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enum dpu_intf blk);
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/**
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* OR in the given flushbits to the cached pending_(merge_3d_)flush_mask
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* No effect on hardware
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* @ctx : ctl path ctx pointer
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* @blk : interface block index
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*/
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void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx,
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enum dpu_merge_3d blk);
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/**
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* Write the value of the pending_flush_mask to hardware
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* @ctx : ctl path ctx pointer
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*/
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void (*trigger_flush)(struct dpu_hw_ctl *ctx);
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/**
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* Read the value of the flush register
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* @ctx : ctl path ctx pointer
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* @Return: value of the ctl flush register.
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*/
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u32 (*get_flush_register)(struct dpu_hw_ctl *ctx);
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/**
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* Setup ctl_path interface config
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* @ctx
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* @cfg : interface config structure pointer
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*/
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void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
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struct dpu_hw_intf_cfg *cfg);
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int (*reset)(struct dpu_hw_ctl *c);
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/*
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* wait_reset_status - checks ctl reset status
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* @ctx : ctl path ctx pointer
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*
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* This function checks the ctl reset status bit.
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* If the reset bit is set, it keeps polling the status till the hw
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* reset is complete.
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* Returns: 0 on success or -error if reset incomplete within interval
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*/
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int (*wait_reset_status)(struct dpu_hw_ctl *ctx);
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uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx,
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enum dpu_sspp blk);
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uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx,
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enum dpu_lm blk);
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uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx,
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enum dpu_dspp blk);
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/**
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* Set all blend stages to disabled
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* @ctx : ctl path ctx pointer
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*/
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void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
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/**
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* Configure layer mixer to pipe configuration
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* @ctx : ctl path ctx pointer
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* @lm : layer mixer enumeration
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* @cfg : blend stage configuration
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*/
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void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
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enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
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void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
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unsigned long *fetch_active);
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};
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/**
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* struct dpu_hw_ctl : CTL PATH driver object
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* @base: hardware block base structure
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* @hw: block register map object
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* @idx: control path index
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* @caps: control path capabilities
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* @mixer_count: number of mixers
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* @mixer_hw_caps: mixer hardware capabilities
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* @pending_flush_mask: storage for pending ctl_flush managed via ops
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* @pending_intf_flush_mask: pending INTF flush
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* @ops: operation list
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*/
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struct dpu_hw_ctl {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* ctl path */
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int idx;
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const struct dpu_ctl_cfg *caps;
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int mixer_count;
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const struct dpu_lm_cfg *mixer_hw_caps;
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u32 pending_flush_mask;
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u32 pending_intf_flush_mask;
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u32 pending_merge_3d_flush_mask;
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/* ops */
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struct dpu_hw_ctl_ops ops;
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};
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/**
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* dpu_hw_ctl - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_ctl, base);
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}
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/**
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* dpu_hw_ctl_init(): Initializes the ctl_path hw driver object.
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* should be called before accessing every ctl path registers.
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* @idx: ctl_path index for which driver object is required
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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*/
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struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
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void __iomem *addr,
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const struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_ctl_destroy(): Destroys ctl driver context
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* should be called to free the context
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*/
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void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx);
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#endif /*_DPU_HW_CTL_H */
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