633 lines
15 KiB
C
633 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/delay.h>
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#include "dpu_hwio.h"
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#include "dpu_hw_ctl.h"
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#include "dpu_kms.h"
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#include "dpu_trace.h"
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#define CTL_LAYER(lm) \
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(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
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#define CTL_LAYER_EXT(lm) \
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(0x40 + (((lm) - LM_0) * 0x004))
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#define CTL_LAYER_EXT2(lm) \
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(0x70 + (((lm) - LM_0) * 0x004))
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#define CTL_LAYER_EXT3(lm) \
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(0xA0 + (((lm) - LM_0) * 0x004))
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#define CTL_TOP 0x014
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#define CTL_FLUSH 0x018
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#define CTL_START 0x01C
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#define CTL_PREPARE 0x0d0
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#define CTL_SW_RESET 0x030
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#define CTL_LAYER_EXTN_OFFSET 0x40
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#define CTL_MERGE_3D_ACTIVE 0x0E4
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#define CTL_INTF_ACTIVE 0x0F4
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#define CTL_MERGE_3D_FLUSH 0x100
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#define CTL_INTF_FLUSH 0x110
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#define CTL_INTF_MASTER 0x134
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#define CTL_FETCH_PIPE_ACTIVE 0x0FC
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#define CTL_MIXER_BORDER_OUT BIT(24)
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#define CTL_FLUSH_MASK_CTL BIT(17)
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#define DPU_REG_RESET_TIMEOUT_US 2000
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#define MERGE_3D_IDX 23
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#define INTF_IDX 31
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#define CTL_INVALID_BIT 0xffff
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#define CTL_DEFAULT_GROUP_ID 0xf
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static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
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CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
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1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
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static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
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const struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->ctl_count; i++) {
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if (ctl == m->ctl[i].id) {
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b->base_off = addr;
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b->blk_off = m->ctl[i].base;
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b->length = m->ctl[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_CTL;
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return &m->ctl[i];
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}
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}
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return ERR_PTR(-ENOMEM);
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}
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static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count,
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enum dpu_lm lm)
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{
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int i;
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int stages = -EINVAL;
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for (i = 0; i < count; i++) {
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if (lm == mixer[i].id) {
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stages = mixer[i].sblk->maxblendstages;
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break;
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}
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}
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return stages;
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}
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static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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return DPU_REG_READ(c, CTL_FLUSH);
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}
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static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
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{
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trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
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}
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static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
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{
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trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
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}
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static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
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{
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trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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ctx->pending_flush_mask = 0x0;
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}
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static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
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u32 flushbits)
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{
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trace_dpu_hw_ctl_update_pending_flush(flushbits,
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ctx->pending_flush_mask);
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ctx->pending_flush_mask |= flushbits;
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}
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static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
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{
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return ctx->pending_flush_mask;
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}
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static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
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{
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if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
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DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
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ctx->pending_merge_3d_flush_mask);
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if (ctx->pending_flush_mask & BIT(INTF_IDX))
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DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
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ctx->pending_intf_flush_mask);
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DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
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}
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static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
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{
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trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
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}
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static uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx,
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enum dpu_sspp sspp)
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{
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uint32_t flushbits = 0;
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switch (sspp) {
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case SSPP_VIG0:
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flushbits = BIT(0);
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break;
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case SSPP_VIG1:
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flushbits = BIT(1);
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break;
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case SSPP_VIG2:
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flushbits = BIT(2);
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break;
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case SSPP_VIG3:
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flushbits = BIT(18);
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break;
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case SSPP_RGB0:
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flushbits = BIT(3);
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break;
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case SSPP_RGB1:
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flushbits = BIT(4);
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break;
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case SSPP_RGB2:
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flushbits = BIT(5);
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break;
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case SSPP_RGB3:
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flushbits = BIT(19);
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break;
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case SSPP_DMA0:
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flushbits = BIT(11);
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break;
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case SSPP_DMA1:
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flushbits = BIT(12);
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break;
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case SSPP_DMA2:
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flushbits = BIT(24);
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break;
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case SSPP_DMA3:
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flushbits = BIT(25);
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break;
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case SSPP_CURSOR0:
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flushbits = BIT(22);
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break;
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case SSPP_CURSOR1:
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flushbits = BIT(23);
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break;
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default:
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break;
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}
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return flushbits;
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}
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static uint32_t dpu_hw_ctl_get_bitmask_mixer(struct dpu_hw_ctl *ctx,
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enum dpu_lm lm)
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{
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uint32_t flushbits = 0;
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switch (lm) {
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case LM_0:
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flushbits = BIT(6);
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break;
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case LM_1:
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flushbits = BIT(7);
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break;
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case LM_2:
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flushbits = BIT(8);
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break;
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case LM_3:
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flushbits = BIT(9);
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break;
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case LM_4:
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flushbits = BIT(10);
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break;
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case LM_5:
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flushbits = BIT(20);
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break;
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default:
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return -EINVAL;
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}
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flushbits |= CTL_FLUSH_MASK_CTL;
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return flushbits;
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}
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static void dpu_hw_ctl_update_pending_flush_intf(struct dpu_hw_ctl *ctx,
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enum dpu_intf intf)
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{
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switch (intf) {
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case INTF_0:
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ctx->pending_flush_mask |= BIT(31);
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break;
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case INTF_1:
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ctx->pending_flush_mask |= BIT(30);
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break;
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case INTF_2:
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ctx->pending_flush_mask |= BIT(29);
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break;
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case INTF_3:
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ctx->pending_flush_mask |= BIT(28);
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break;
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default:
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break;
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}
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}
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static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx,
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enum dpu_intf intf)
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{
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ctx->pending_intf_flush_mask |= BIT(intf - INTF_0);
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ctx->pending_flush_mask |= BIT(INTF_IDX);
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}
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static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
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enum dpu_merge_3d merge_3d)
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{
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ctx->pending_merge_3d_flush_mask |= BIT(merge_3d - MERGE_3D_0);
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ctx->pending_flush_mask |= BIT(MERGE_3D_IDX);
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}
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static uint32_t dpu_hw_ctl_get_bitmask_dspp(struct dpu_hw_ctl *ctx,
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enum dpu_dspp dspp)
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{
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uint32_t flushbits = 0;
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switch (dspp) {
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case DSPP_0:
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flushbits = BIT(13);
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break;
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case DSPP_1:
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flushbits = BIT(14);
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break;
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case DSPP_2:
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flushbits = BIT(15);
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break;
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case DSPP_3:
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flushbits = BIT(21);
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break;
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default:
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return 0;
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}
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return flushbits;
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}
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static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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ktime_t timeout;
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u32 status;
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timeout = ktime_add_us(ktime_get(), timeout_us);
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/*
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* it takes around 30us to have mdp finish resetting its ctl path
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* poll every 50us so that reset should be completed at 1st poll
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*/
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do {
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status = DPU_REG_READ(c, CTL_SW_RESET);
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status &= 0x1;
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if (status)
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usleep_range(20, 50);
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} while (status && ktime_compare_safe(ktime_get(), timeout) < 0);
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return status;
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}
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static int dpu_hw_ctl_reset_control(struct dpu_hw_ctl *ctx)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx);
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DPU_REG_WRITE(c, CTL_SW_RESET, 0x1);
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if (dpu_hw_ctl_poll_reset_status(ctx, DPU_REG_RESET_TIMEOUT_US))
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return -EINVAL;
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return 0;
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}
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static int dpu_hw_ctl_wait_reset_status(struct dpu_hw_ctl *ctx)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 status;
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status = DPU_REG_READ(c, CTL_SW_RESET);
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status &= 0x01;
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if (!status)
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return 0;
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pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx);
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if (dpu_hw_ctl_poll_reset_status(ctx, DPU_REG_RESET_TIMEOUT_US)) {
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pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx);
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return -EINVAL;
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}
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return 0;
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}
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static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int i;
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for (i = 0; i < ctx->mixer_count; i++) {
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enum dpu_lm mixer_id = ctx->mixer_hw_caps[i].id;
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DPU_REG_WRITE(c, CTL_LAYER(mixer_id), 0);
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DPU_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
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DPU_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
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DPU_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
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}
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DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
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}
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static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
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enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 mixercfg = 0, mixercfg_ext = 0, mix, ext;
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u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0;
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int i, j;
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int stages;
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int pipes_per_stage;
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stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
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if (stages < 0)
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return;
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if (test_bit(DPU_MIXER_SOURCESPLIT,
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&ctx->mixer_hw_caps->features))
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pipes_per_stage = PIPES_PER_STAGE;
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else
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pipes_per_stage = 1;
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mixercfg = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */
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if (!stage_cfg)
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goto exit;
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for (i = 0; i <= stages; i++) {
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/* overflow to ext register if 'i + 1 > 7' */
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mix = (i + 1) & 0x7;
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ext = i >= 7;
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for (j = 0 ; j < pipes_per_stage; j++) {
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enum dpu_sspp_multirect_index rect_index =
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stage_cfg->multirect_index[i][j];
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switch (stage_cfg->stage[i][j]) {
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case SSPP_VIG0:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext3 |= ((i + 1) & 0xF) << 0;
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} else {
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mixercfg |= mix << 0;
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mixercfg_ext |= ext << 0;
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}
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break;
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case SSPP_VIG1:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext3 |= ((i + 1) & 0xF) << 4;
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} else {
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mixercfg |= mix << 3;
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mixercfg_ext |= ext << 2;
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}
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break;
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case SSPP_VIG2:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext3 |= ((i + 1) & 0xF) << 8;
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} else {
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mixercfg |= mix << 6;
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mixercfg_ext |= ext << 4;
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}
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break;
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case SSPP_VIG3:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext3 |= ((i + 1) & 0xF) << 12;
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} else {
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mixercfg |= mix << 26;
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mixercfg_ext |= ext << 6;
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}
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break;
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case SSPP_RGB0:
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mixercfg |= mix << 9;
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mixercfg_ext |= ext << 8;
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break;
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case SSPP_RGB1:
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mixercfg |= mix << 12;
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mixercfg_ext |= ext << 10;
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break;
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case SSPP_RGB2:
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mixercfg |= mix << 15;
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mixercfg_ext |= ext << 12;
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break;
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case SSPP_RGB3:
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mixercfg |= mix << 29;
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mixercfg_ext |= ext << 14;
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break;
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case SSPP_DMA0:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext2 |= ((i + 1) & 0xF) << 8;
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} else {
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mixercfg |= mix << 18;
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mixercfg_ext |= ext << 16;
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}
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break;
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case SSPP_DMA1:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext2 |= ((i + 1) & 0xF) << 12;
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} else {
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mixercfg |= mix << 21;
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mixercfg_ext |= ext << 18;
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}
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break;
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case SSPP_DMA2:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext2 |= ((i + 1) & 0xF) << 16;
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} else {
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mix |= (i + 1) & 0xF;
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mixercfg_ext2 |= mix << 0;
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}
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break;
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case SSPP_DMA3:
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if (rect_index == DPU_SSPP_RECT_1) {
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mixercfg_ext2 |= ((i + 1) & 0xF) << 20;
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} else {
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mix |= (i + 1) & 0xF;
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mixercfg_ext2 |= mix << 4;
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}
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break;
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case SSPP_CURSOR0:
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mixercfg_ext |= ((i + 1) & 0xF) << 20;
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break;
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case SSPP_CURSOR1:
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mixercfg_ext |= ((i + 1) & 0xF) << 26;
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break;
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default:
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break;
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}
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}
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}
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exit:
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DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
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DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
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DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);
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DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
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}
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static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
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struct dpu_hw_intf_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 intf_active = 0;
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u32 mode_sel = 0;
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/* CTL_TOP[31:28] carries group_id to collate CTL paths
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* per VM. Explicitly disable it until VM support is
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* added in SW. Power on reset value is not disable.
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*/
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if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
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mode_sel = CTL_DEFAULT_GROUP_ID << 28;
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if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
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mode_sel |= BIT(17);
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intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
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intf_active |= BIT(cfg->intf - INTF_0);
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DPU_REG_WRITE(c, CTL_TOP, mode_sel);
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DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
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if (cfg->merge_3d)
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DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
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BIT(cfg->merge_3d - MERGE_3D_0));
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}
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static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
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struct dpu_hw_intf_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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u32 intf_cfg = 0;
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intf_cfg |= (cfg->intf & 0xF) << 4;
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if (cfg->mode_3d) {
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intf_cfg |= BIT(19);
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intf_cfg |= (cfg->mode_3d - 0x1) << 20;
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}
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switch (cfg->intf_mode_sel) {
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case DPU_CTL_MODE_SEL_VID:
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intf_cfg &= ~BIT(17);
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intf_cfg &= ~(0x3 << 15);
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break;
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case DPU_CTL_MODE_SEL_CMD:
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intf_cfg |= BIT(17);
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intf_cfg |= ((cfg->stream_sel & 0x3) << 15);
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break;
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default:
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pr_err("unknown interface type %d\n", cfg->intf_mode_sel);
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return;
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}
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DPU_REG_WRITE(c, CTL_TOP, intf_cfg);
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}
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static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,
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unsigned long *fetch_active)
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{
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int i;
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u32 val = 0;
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if (fetch_active) {
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for (i = 0; i < SSPP_MAX; i++) {
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if (test_bit(i, fetch_active) &&
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fetch_tbl[i] != CTL_INVALID_BIT)
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val |= BIT(fetch_tbl[i]);
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}
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}
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DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
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}
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static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
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unsigned long cap)
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{
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if (cap & BIT(DPU_CTL_ACTIVE_CFG)) {
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ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1;
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ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
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ops->update_pending_flush_intf =
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dpu_hw_ctl_update_pending_flush_intf_v1;
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ops->update_pending_flush_merge_3d =
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dpu_hw_ctl_update_pending_flush_merge_3d_v1;
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} else {
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ops->trigger_flush = dpu_hw_ctl_trigger_flush;
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ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
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ops->update_pending_flush_intf =
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dpu_hw_ctl_update_pending_flush_intf;
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}
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ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
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ops->update_pending_flush = dpu_hw_ctl_update_pending_flush;
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ops->get_pending_flush = dpu_hw_ctl_get_pending_flush;
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ops->get_flush_register = dpu_hw_ctl_get_flush_register;
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ops->trigger_start = dpu_hw_ctl_trigger_start;
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ops->trigger_pending = dpu_hw_ctl_trigger_pending;
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ops->reset = dpu_hw_ctl_reset_control;
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ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
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ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
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ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
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ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
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ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
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ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp;
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if (cap & BIT(DPU_CTL_FETCH_ACTIVE))
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ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active;
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};
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struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
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void __iomem *addr,
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const struct dpu_mdss_cfg *m)
|
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{
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struct dpu_hw_ctl *c;
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const struct dpu_ctl_cfg *cfg;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _ctl_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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pr_err("failed to create dpu_hw_ctl %d\n", idx);
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return ERR_PTR(-EINVAL);
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}
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|
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c->caps = cfg;
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_setup_ctl_ops(&c->ops, c->caps->features);
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c->idx = idx;
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c->mixer_count = m->mixer_count;
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c->mixer_hw_caps = m->mixer;
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return c;
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}
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void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx)
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{
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kfree(ctx);
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}
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