199 lines
6.6 KiB
C
199 lines
6.6 KiB
C
/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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*
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* S5PC1XX - Common IRQ support
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*
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* Based on plat-s3c64xx/include/plat/irqs.h
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*/
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#ifndef __ASM_PLAT_S5PC1XX_IRQS_H
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#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*
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* note, since we're using the VICs, our start must be a
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* mulitple of 32 to allow the common code to work
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*/
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#define S3C_IRQ_OFFSET (32)
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#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
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#define S3C_VIC0_BASE S3C_IRQ(0)
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#define S3C_VIC1_BASE S3C_IRQ(32)
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#define S3C_VIC2_BASE S3C_IRQ(64)
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/* UART interrupts, each UART has 4 intterupts per channel so
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* use the space between the ISA and S3C main interrupts. Note, these
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* are not in the same order as the S3C24XX series! */
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#define IRQ_S3CUART_BASE0 (16)
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#define IRQ_S3CUART_BASE1 (20)
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#define IRQ_S3CUART_BASE2 (24)
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#define IRQ_S3CUART_BASE3 (28)
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#define UART_IRQ_RXD (0)
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#define UART_IRQ_ERR (1)
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#define UART_IRQ_TXD (2)
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#define UART_IRQ_MODEM (3)
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#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
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/* VIC based IRQs */
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#define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
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#define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
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#define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x))
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/*
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* VIC0: system, DMA, timer
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*/
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#define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0)
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#define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1)
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#define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2)
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#define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3)
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#define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4)
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#define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5)
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#define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6)
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#define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7)
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#define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8)
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#define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9)
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#define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10)
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#define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11)
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#define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12)
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#define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13)
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#define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14)
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#define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15)
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#define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16)
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#define IRQ_BATF S5PC1XX_IRQ_VIC0(17)
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#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18)
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#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19)
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#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20)
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#define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21)
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#define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22)
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#define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23)
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#define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24)
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#define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25)
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#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26)
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#define IRQ_WDT S5PC1XX_IRQ_VIC0(27)
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#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28)
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#define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29)
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#define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30)
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/*
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* VIC1: ARM, power, memory, connectivity
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*/
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#define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0)
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#define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1)
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#define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2)
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#define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3)
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#define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4)
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#define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5)
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#define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6)
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#define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7)
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#define IRQ_NFC S5PC1XX_IRQ_VIC1(8)
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#define IRQ_CFC S5PC1XX_IRQ_VIC1(9)
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#define IRQ_UART0 S5PC1XX_IRQ_VIC1(10)
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#define IRQ_UART1 S5PC1XX_IRQ_VIC1(11)
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#define IRQ_UART2 S5PC1XX_IRQ_VIC1(12)
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#define IRQ_UART3 S5PC1XX_IRQ_VIC1(13)
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#define IRQ_IIC S5PC1XX_IRQ_VIC1(14)
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#define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15)
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#define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16)
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#define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17)
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#define IRQ_IRDA S5PC1XX_IRQ_VIC1(18)
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#define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19)
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#define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20)
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#define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21)
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#define IRQ_HSITX S5PC1XX_IRQ_VIC1(22)
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#define IRQ_UHOST S5PC1XX_IRQ_VIC1(23)
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#define IRQ_OTG S5PC1XX_IRQ_VIC1(24)
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#define IRQ_MSM S5PC1XX_IRQ_VIC1(25)
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#define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26)
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#define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27)
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#define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28)
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#define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29)
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#define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30)
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/*
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* VIC2: multimedia, audio, security
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*/
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#define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0)
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#define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1)
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#define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2)
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#define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3)
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#define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4)
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#define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5)
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#define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6)
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#define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7)
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#define IRQ_JPEG S5PC1XX_IRQ_VIC2(8)
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#define IRQ_2D S5PC1XX_IRQ_VIC2(9)
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#define IRQ_3D S5PC1XX_IRQ_VIC2(10)
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#define IRQ_MIXER S5PC1XX_IRQ_VIC2(11)
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#define IRQ_HDMI S5PC1XX_IRQ_VIC2(12)
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#define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13)
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#define IRQ_MFC S5PC1XX_IRQ_VIC2(14)
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#define IRQ_TVENC S5PC1XX_IRQ_VIC2(15)
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#define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16)
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#define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17)
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#define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18)
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#define IRQ_AC97 S5PC1XX_IRQ_VIC2(19)
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#define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20)
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#define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21)
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#define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22)
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#define IRQ_ADC S5PC1XX_IRQ_VIC2(23)
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#define IRQ_PENDN S5PC1XX_IRQ_VIC2(24)
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#define IRQ_TC IRQ_PENDN
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#define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25)
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#define IRQ_CG S5PC1XX_IRQ_VIC2(26)
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#define IRQ_SEC S5PC1XX_IRQ_VIC2(27)
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#define IRQ_SECRX S5PC1XX_IRQ_VIC2(28)
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#define IRQ_SECTX S5PC1XX_IRQ_VIC2(29)
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#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30)
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#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31)
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#define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x))
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#define IRQ_TIMER0 IRQ_TIMER(0)
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#define IRQ_TIMER1 IRQ_TIMER(1)
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#define IRQ_TIMER2 IRQ_TIMER(2)
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#define IRQ_TIMER3 IRQ_TIMER(3)
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#define IRQ_TIMER4 IRQ_TIMER(4)
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/* External interrupt */
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#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6)
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#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16))
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#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
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#define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
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/* GPIO interrupt */
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#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
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#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
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/*
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* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
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*/
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#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
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#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
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