366 lines
11 KiB
C
366 lines
11 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv04.h"
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#include <core/client.h>
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#include <core/engctx.h>
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#include <core/ramht.h>
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#include <subdev/fb.h>
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#include <subdev/instmem.h>
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#include <nvif/class.h>
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#include <nvif/unpack.h>
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static struct ramfc_desc
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nv40_ramfc[] = {
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{ 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
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{ 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
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{ 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
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{ 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
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{ 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
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{ 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE },
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{ 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
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{ 2, 28, 0x18, 28, 0x002058 },
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{ 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE },
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{ 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 },
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{ 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
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{ 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
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{ 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
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{ 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE },
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{ 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
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{ 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE },
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{ 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE },
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{ 32, 0, 0x40, 0, 0x0032e4 },
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{ 32, 0, 0x44, 0, 0x0032e8 },
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{ 32, 0, 0x4c, 0, 0x002088 },
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{ 32, 0, 0x50, 0, 0x003300 },
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{ 32, 0, 0x54, 0, 0x00330c },
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{}
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};
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/*******************************************************************************
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* FIFO channel objects
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******************************************************************************/
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static int
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nv40_fifo_object_attach(struct nvkm_object *parent,
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struct nvkm_object *object, u32 handle)
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{
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struct nv04_fifo *fifo = (void *)parent->engine;
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struct nv04_fifo_chan *chan = (void *)parent;
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u32 context, chid = chan->base.chid;
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int ret;
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if (nv_iclass(object, NV_GPUOBJ_CLASS))
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context = nv_gpuobj(object)->addr >> 4;
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else
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context = 0x00000004; /* just non-zero */
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switch (nv_engidx(object->engine)) {
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case NVDEV_ENGINE_DMAOBJ:
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case NVDEV_ENGINE_SW:
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context |= 0x00000000;
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break;
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case NVDEV_ENGINE_GR:
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context |= 0x00100000;
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break;
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case NVDEV_ENGINE_MPEG:
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context |= 0x00200000;
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break;
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default:
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return -EINVAL;
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}
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context |= chid << 23;
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mutex_lock(&nv_subdev(fifo)->mutex);
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ret = nvkm_ramht_insert(fifo->ramht, chid, handle, context);
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mutex_unlock(&nv_subdev(fifo)->mutex);
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return ret;
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}
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static int
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nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx)
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{
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struct nv04_fifo *fifo = (void *)parent->engine;
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struct nv04_fifo_chan *chan = (void *)parent;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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unsigned long flags;
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u32 reg, ctx;
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switch (nv_engidx(engctx->engine)) {
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case NVDEV_ENGINE_SW:
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return 0;
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case NVDEV_ENGINE_GR:
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reg = 0x32e0;
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ctx = 0x38;
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break;
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case NVDEV_ENGINE_MPEG:
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reg = 0x330c;
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ctx = 0x54;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&fifo->base.lock, flags);
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nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
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nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
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if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid)
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nvkm_wr32(device, reg, nv_engctx(engctx)->addr);
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nvkm_kmap(fifo->ramfc);
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nvkm_wo32(fifo->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
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nvkm_done(fifo->ramfc);
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nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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return 0;
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}
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static int
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nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend,
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struct nvkm_object *engctx)
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{
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struct nv04_fifo *fifo = (void *)parent->engine;
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struct nv04_fifo_chan *chan = (void *)parent;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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unsigned long flags;
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u32 reg, ctx;
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switch (nv_engidx(engctx->engine)) {
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case NVDEV_ENGINE_SW:
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return 0;
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case NVDEV_ENGINE_GR:
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reg = 0x32e0;
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ctx = 0x38;
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break;
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case NVDEV_ENGINE_MPEG:
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reg = 0x330c;
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ctx = 0x54;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&fifo->base.lock, flags);
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nvkm_mask(device, 0x002500, 0x00000001, 0x00000000);
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if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid)
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nvkm_wr32(device, reg, 0x00000000);
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nvkm_kmap(fifo->ramfc);
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nvkm_wo32(fifo->ramfc, chan->ramfc + ctx, 0x00000000);
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nvkm_done(fifo->ramfc);
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nvkm_mask(device, 0x002500, 0x00000001, 0x00000001);
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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return 0;
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}
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static int
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nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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union {
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struct nv03_channel_dma_v0 v0;
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} *args = data;
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struct nv04_fifo *fifo = (void *)engine;
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struct nv04_fifo_chan *chan;
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int ret;
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nvif_ioctl(parent, "create channel dma size %d\n", size);
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if (nvif_unpack(args->v0, 0, 0, false)) {
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nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
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"offset %08x\n", args->v0.version,
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args->v0.pushbuf, args->v0.offset);
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} else
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return ret;
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ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
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0x1000, args->v0.pushbuf,
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(1ULL << NVDEV_ENGINE_DMAOBJ) |
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(1ULL << NVDEV_ENGINE_SW) |
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(1ULL << NVDEV_ENGINE_GR) |
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(1ULL << NVDEV_ENGINE_MPEG), &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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args->v0.chid = chan->base.chid;
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nv_parent(chan)->context_attach = nv40_fifo_context_attach;
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nv_parent(chan)->context_detach = nv40_fifo_context_detach;
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nv_parent(chan)->object_attach = nv40_fifo_object_attach;
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nv_parent(chan)->object_detach = nv04_fifo_object_detach;
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chan->ramfc = chan->base.chid * 128;
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nvkm_kmap(fifo->ramfc);
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nvkm_wo32(fifo->ramfc, chan->ramfc + 0x00, args->v0.offset);
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nvkm_wo32(fifo->ramfc, chan->ramfc + 0x04, args->v0.offset);
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nvkm_wo32(fifo->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
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nvkm_wo32(fifo->ramfc, chan->ramfc + 0x18, 0x30000000 |
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NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
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nvkm_wo32(fifo->ramfc, chan->ramfc + 0x3c, 0x0001ffff);
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nvkm_done(fifo->ramfc);
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return 0;
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}
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static struct nvkm_ofuncs
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nv40_fifo_ofuncs = {
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.ctor = nv40_fifo_chan_ctor,
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.dtor = nv04_fifo_chan_dtor,
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.init = nv04_fifo_chan_init,
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.fini = nv04_fifo_chan_fini,
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.map = _nvkm_fifo_channel_map,
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.rd32 = _nvkm_fifo_channel_rd32,
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.wr32 = _nvkm_fifo_channel_wr32,
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.ntfy = _nvkm_fifo_channel_ntfy
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};
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static struct nvkm_oclass
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nv40_fifo_sclass[] = {
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{ NV40_CHANNEL_DMA, &nv40_fifo_ofuncs },
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{}
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};
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/*******************************************************************************
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* FIFO context - basically just the instmem reserved for the channel
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******************************************************************************/
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static struct nvkm_oclass
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nv40_fifo_cclass = {
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.handle = NV_ENGCTX(FIFO, 0x40),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv04_fifo_context_ctor,
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.dtor = _nvkm_fifo_context_dtor,
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.init = _nvkm_fifo_context_init,
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.fini = _nvkm_fifo_context_fini,
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.rd32 = _nvkm_fifo_context_rd32,
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.wr32 = _nvkm_fifo_context_wr32,
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},
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};
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/*******************************************************************************
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* PFIFO engine
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******************************************************************************/
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static int
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nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nvkm_device *device = (void *)parent;
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struct nvkm_instmem *imem = device->imem;
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struct nv04_fifo *fifo;
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int ret;
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ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
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*pobject = nv_object(fifo);
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if (ret)
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return ret;
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nvkm_ramht_ref(imem->ramht, &fifo->ramht);
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nvkm_gpuobj_ref(imem->ramro, &fifo->ramro);
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nvkm_gpuobj_ref(imem->ramfc, &fifo->ramfc);
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nv_subdev(fifo)->unit = 0x00000100;
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nv_subdev(fifo)->intr = nv04_fifo_intr;
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nv_engine(fifo)->cclass = &nv40_fifo_cclass;
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nv_engine(fifo)->sclass = nv40_fifo_sclass;
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fifo->base.pause = nv04_fifo_pause;
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fifo->base.start = nv04_fifo_start;
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fifo->ramfc_desc = nv40_ramfc;
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return 0;
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}
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static int
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nv40_fifo_init(struct nvkm_object *object)
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{
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struct nv04_fifo *fifo = (void *)object;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_fb *fb = device->fb;
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int ret;
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ret = nvkm_fifo_init(&fifo->base);
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if (ret)
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return ret;
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nvkm_wr32(device, 0x002040, 0x000000ff);
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nvkm_wr32(device, 0x002044, 0x2101ffff);
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nvkm_wr32(device, 0x002058, 0x00000001);
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nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
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((fifo->ramht->bits - 9) << 16) |
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(fifo->ramht->gpuobj.addr >> 8));
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nvkm_wr32(device, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8);
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switch (nv_device(fifo)->chipset) {
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case 0x47:
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case 0x49:
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case 0x4b:
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nvkm_wr32(device, 0x002230, 0x00000001);
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x45:
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case 0x48:
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nvkm_wr32(device, 0x002220, 0x00030002);
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break;
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default:
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nvkm_wr32(device, 0x002230, 0x00000000);
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nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +
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fifo->ramfc->addr) >> 16) |
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0x00030000);
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break;
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}
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max);
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nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
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nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
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nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
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nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
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return 0;
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}
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struct nvkm_oclass *
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nv40_fifo_oclass = &(struct nvkm_oclass) {
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.handle = NV_ENGINE(FIFO, 0x40),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv40_fifo_ctor,
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.dtor = nv04_fifo_dtor,
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.init = nv40_fifo_init,
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.fini = _nvkm_fifo_fini,
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},
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};
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