992 lines
27 KiB
C
992 lines
27 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <engine/fifo.h>
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#include <core/client.h>
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#include <core/engctx.h>
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#include <core/enum.h>
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#include <core/handle.h>
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#include <subdev/fb.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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#include <nvif/ioctl.h>
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#include <nvif/unpack.h>
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struct gf100_fifo {
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struct nvkm_fifo base;
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struct work_struct fault;
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u64 mask;
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struct {
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struct nvkm_gpuobj *mem[2];
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int active;
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wait_queue_head_t wait;
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} runlist;
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struct {
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struct nvkm_gpuobj *mem;
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struct nvkm_vma bar;
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} user;
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int spoon_nr;
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};
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struct gf100_fifo_base {
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struct nvkm_fifo_base base;
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struct nvkm_gpuobj *pgd;
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struct nvkm_vm *vm;
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};
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struct gf100_fifo_chan {
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struct nvkm_fifo_chan base;
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enum {
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STOPPED,
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RUNNING,
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KILLED
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} state;
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};
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/*******************************************************************************
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* FIFO channel objects
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******************************************************************************/
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static void
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gf100_fifo_runlist_update(struct gf100_fifo *fifo)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_gpuobj *cur;
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int i, p;
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mutex_lock(&nv_subdev(fifo)->mutex);
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cur = fifo->runlist.mem[fifo->runlist.active];
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fifo->runlist.active = !fifo->runlist.active;
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nvkm_kmap(cur);
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for (i = 0, p = 0; i < 128; i++) {
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struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i];
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if (chan && chan->state == RUNNING) {
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nvkm_wo32(cur, p + 0, i);
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nvkm_wo32(cur, p + 4, 0x00000004);
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p += 8;
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}
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}
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nvkm_done(cur);
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nvkm_wr32(device, 0x002270, cur->addr >> 12);
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nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3));
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if (wait_event_timeout(fifo->runlist.wait,
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!(nvkm_rd32(device, 0x00227c) & 0x00100000),
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msecs_to_jiffies(2000)) == 0)
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nvkm_error(subdev, "runlist update timeout\n");
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mutex_unlock(&nv_subdev(fifo)->mutex);
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}
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static int
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gf100_fifo_context_attach(struct nvkm_object *parent,
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struct nvkm_object *object)
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{
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struct gf100_fifo_base *base = (void *)parent->parent;
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struct nvkm_gpuobj *engn = &base->base.gpuobj;
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struct nvkm_engctx *ectx = (void *)object;
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u32 addr;
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int ret;
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switch (nv_engidx(object->engine)) {
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case NVDEV_ENGINE_SW : return 0;
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case NVDEV_ENGINE_GR : addr = 0x0210; break;
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case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
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case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
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case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
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case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
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case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
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default:
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return -EINVAL;
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}
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if (!ectx->vma.node) {
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ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
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NV_MEM_ACCESS_RW, &ectx->vma);
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if (ret)
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return ret;
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nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
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}
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nvkm_kmap(engn);
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nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
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nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset));
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nvkm_done(engn);
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return 0;
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}
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static int
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gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend,
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struct nvkm_object *object)
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{
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struct gf100_fifo *fifo = (void *)parent->engine;
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struct gf100_fifo_base *base = (void *)parent->parent;
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struct gf100_fifo_chan *chan = (void *)parent;
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struct nvkm_gpuobj *engn = &base->base.gpuobj;
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 addr;
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switch (nv_engidx(object->engine)) {
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case NVDEV_ENGINE_SW : return 0;
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case NVDEV_ENGINE_GR : addr = 0x0210; break;
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case NVDEV_ENGINE_CE0 : addr = 0x0230; break;
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case NVDEV_ENGINE_CE1 : addr = 0x0240; break;
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case NVDEV_ENGINE_MSVLD : addr = 0x0270; break;
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case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break;
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case NVDEV_ENGINE_MSPPP : addr = 0x0260; break;
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default:
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return -EINVAL;
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}
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nvkm_wr32(device, 0x002634, chan->base.chid);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x002634) == chan->base.chid)
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break;
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) < 0) {
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nvkm_error(subdev, "channel %d [%s] kick timeout\n",
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chan->base.chid, nvkm_client_name(chan));
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if (suspend)
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return -EBUSY;
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}
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nvkm_kmap(engn);
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nvkm_wo32(engn, addr + 0x00, 0x00000000);
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nvkm_wo32(engn, addr + 0x04, 0x00000000);
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nvkm_done(engn);
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return 0;
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}
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static int
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gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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union {
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struct fermi_channel_gpfifo_v0 v0;
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} *args = data;
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struct gf100_fifo *fifo = (void *)engine;
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struct gf100_fifo_base *base = (void *)parent;
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struct gf100_fifo_chan *chan;
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struct nvkm_gpuobj *ramfc = &base->base.gpuobj;
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u64 usermem, ioffset, ilength;
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int ret, i;
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nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
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if (nvif_unpack(args->v0, 0, 0, false)) {
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nvif_ioctl(parent, "create channel gpfifo vers %d "
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"ioffset %016llx ilength %08x\n",
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args->v0.version, args->v0.ioffset,
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args->v0.ilength);
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if (args->v0.vm)
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return -ENOENT;
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} else
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return ret;
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ret = nvkm_fifo_channel_create(parent, engine, oclass, 1,
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fifo->user.bar.offset, 0x1000, 0,
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(1ULL << NVDEV_ENGINE_SW) |
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(1ULL << NVDEV_ENGINE_GR) |
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(1ULL << NVDEV_ENGINE_CE0) |
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(1ULL << NVDEV_ENGINE_CE1) |
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(1ULL << NVDEV_ENGINE_MSVLD) |
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(1ULL << NVDEV_ENGINE_MSPDEC) |
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(1ULL << NVDEV_ENGINE_MSPPP), &chan);
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*pobject = nv_object(chan);
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if (ret)
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return ret;
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args->v0.chid = chan->base.chid;
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nv_parent(chan)->context_attach = gf100_fifo_context_attach;
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nv_parent(chan)->context_detach = gf100_fifo_context_detach;
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usermem = chan->base.chid * 0x1000;
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ioffset = args->v0.ioffset;
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ilength = order_base_2(args->v0.ilength / 8);
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nvkm_kmap(fifo->user.mem);
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for (i = 0; i < 0x1000; i += 4)
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nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
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nvkm_done(fifo->user.mem);
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nvkm_kmap(ramfc);
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nvkm_wo32(ramfc, 0x08, lower_32_bits(fifo->user.mem->addr + usermem));
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nvkm_wo32(ramfc, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem));
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nvkm_wo32(ramfc, 0x10, 0x0000face);
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nvkm_wo32(ramfc, 0x30, 0xfffff902);
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nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset));
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nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
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nvkm_wo32(ramfc, 0x54, 0x00000002);
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nvkm_wo32(ramfc, 0x84, 0x20400000);
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nvkm_wo32(ramfc, 0x94, 0x30000001);
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nvkm_wo32(ramfc, 0x9c, 0x00000100);
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nvkm_wo32(ramfc, 0xa4, 0x1f1f1f1f);
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nvkm_wo32(ramfc, 0xa8, 0x1f1f1f1f);
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nvkm_wo32(ramfc, 0xac, 0x0000001f);
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nvkm_wo32(ramfc, 0xb8, 0xf8000000);
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nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */
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nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */
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nvkm_done(ramfc);
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return 0;
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}
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static int
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gf100_fifo_chan_init(struct nvkm_object *object)
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{
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struct nvkm_gpuobj *base = nv_gpuobj(object->parent);
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struct gf100_fifo *fifo = (void *)object->engine;
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struct gf100_fifo_chan *chan = (void *)object;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 chid = chan->base.chid;
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int ret;
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ret = nvkm_fifo_channel_init(&chan->base);
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if (ret)
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return ret;
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nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
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if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
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nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001);
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gf100_fifo_runlist_update(fifo);
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}
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return 0;
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}
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static void gf100_fifo_intr_engine(struct gf100_fifo *fifo);
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static int
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gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend)
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{
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struct gf100_fifo *fifo = (void *)object->engine;
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struct gf100_fifo_chan *chan = (void *)object;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 chid = chan->base.chid;
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if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
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nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
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gf100_fifo_runlist_update(fifo);
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}
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gf100_fifo_intr_engine(fifo);
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nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000);
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return nvkm_fifo_channel_fini(&chan->base, suspend);
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}
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static struct nvkm_ofuncs
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gf100_fifo_ofuncs = {
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.ctor = gf100_fifo_chan_ctor,
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.dtor = _nvkm_fifo_channel_dtor,
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.init = gf100_fifo_chan_init,
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.fini = gf100_fifo_chan_fini,
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.map = _nvkm_fifo_channel_map,
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.rd32 = _nvkm_fifo_channel_rd32,
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.wr32 = _nvkm_fifo_channel_wr32,
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.ntfy = _nvkm_fifo_channel_ntfy
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};
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static struct nvkm_oclass
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gf100_fifo_sclass[] = {
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{ FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs },
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{}
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};
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/*******************************************************************************
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* FIFO context - instmem heap and vm setup
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******************************************************************************/
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static int
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gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct gf100_fifo_base *base;
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int ret;
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ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
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0x1000, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_HEAP, &base);
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*pobject = nv_object(base);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
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&base->pgd);
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if (ret)
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return ret;
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nvkm_kmap(&base->base.gpuobj);
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nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr));
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nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr));
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nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff);
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nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff);
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nvkm_done(&base->base.gpuobj);
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ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
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if (ret)
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return ret;
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return 0;
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}
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static void
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gf100_fifo_context_dtor(struct nvkm_object *object)
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{
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struct gf100_fifo_base *base = (void *)object;
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nvkm_vm_ref(NULL, &base->vm, base->pgd);
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nvkm_gpuobj_ref(NULL, &base->pgd);
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nvkm_fifo_context_destroy(&base->base);
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}
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static struct nvkm_oclass
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gf100_fifo_cclass = {
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.handle = NV_ENGCTX(FIFO, 0xc0),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = gf100_fifo_context_ctor,
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.dtor = gf100_fifo_context_dtor,
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.init = _nvkm_fifo_context_init,
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.fini = _nvkm_fifo_context_fini,
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.rd32 = _nvkm_fifo_context_rd32,
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.wr32 = _nvkm_fifo_context_wr32,
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},
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};
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/*******************************************************************************
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* PFIFO engine
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******************************************************************************/
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static inline int
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gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
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{
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switch (engn) {
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case NVDEV_ENGINE_GR : engn = 0; break;
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case NVDEV_ENGINE_MSVLD : engn = 1; break;
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case NVDEV_ENGINE_MSPPP : engn = 2; break;
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case NVDEV_ENGINE_MSPDEC: engn = 3; break;
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case NVDEV_ENGINE_CE0 : engn = 4; break;
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case NVDEV_ENGINE_CE1 : engn = 5; break;
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default:
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return -1;
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}
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return engn;
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}
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static inline struct nvkm_engine *
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gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
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{
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switch (engn) {
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case 0: engn = NVDEV_ENGINE_GR; break;
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case 1: engn = NVDEV_ENGINE_MSVLD; break;
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case 2: engn = NVDEV_ENGINE_MSPPP; break;
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case 3: engn = NVDEV_ENGINE_MSPDEC; break;
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case 4: engn = NVDEV_ENGINE_CE0; break;
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case 5: engn = NVDEV_ENGINE_CE1; break;
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default:
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return NULL;
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}
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return nvkm_engine(fifo, engn);
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}
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static void
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gf100_fifo_recover_work(struct work_struct *work)
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{
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struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault);
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_engine *engine;
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unsigned long flags;
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u32 engn, engm = 0;
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u64 mask, todo;
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spin_lock_irqsave(&fifo->base.lock, flags);
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mask = fifo->mask;
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fifo->mask = 0ULL;
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
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engm |= 1 << gf100_fifo_engidx(fifo, engn);
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nvkm_mask(device, 0x002630, engm, engm);
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for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
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if ((engine = nvkm_device_engine(device, engn))) {
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nvkm_subdev_fini(&engine->subdev, false);
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WARN_ON(nvkm_subdev_init(&engine->subdev));
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}
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}
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gf100_fifo_runlist_update(fifo);
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nvkm_wr32(device, 0x00262c, engm);
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nvkm_mask(device, 0x002630, engm, 0x00000000);
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}
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static void
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gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
|
|
struct gf100_fifo_chan *chan)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 chid = chan->base.chid;
|
|
unsigned long flags;
|
|
|
|
nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
|
|
nvkm_subdev_name[engine->subdev.index], chid);
|
|
|
|
nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
|
|
chan->state = KILLED;
|
|
|
|
spin_lock_irqsave(&fifo->base.lock, flags);
|
|
fifo->mask |= 1ULL << nv_engidx(engine);
|
|
spin_unlock_irqrestore(&fifo->base.lock, flags);
|
|
schedule_work(&fifo->fault);
|
|
}
|
|
|
|
static int
|
|
gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data)
|
|
{
|
|
struct gf100_fifo_chan *chan = NULL;
|
|
struct nvkm_handle *bind;
|
|
unsigned long flags;
|
|
int ret = -EINVAL;
|
|
|
|
spin_lock_irqsave(&fifo->base.lock, flags);
|
|
if (likely(chid >= fifo->base.min && chid <= fifo->base.max))
|
|
chan = (void *)fifo->base.channel[chid];
|
|
if (unlikely(!chan))
|
|
goto out;
|
|
|
|
bind = nvkm_namedb_get_class(nv_namedb(chan), NVIF_IOCTL_NEW_V0_SW_GF100);
|
|
if (likely(bind)) {
|
|
if (!mthd || !nv_call(bind->object, mthd, data))
|
|
ret = 0;
|
|
nvkm_namedb_put(bind);
|
|
}
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&fifo->base.lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static const struct nvkm_enum
|
|
gf100_fifo_sched_reason[] = {
|
|
{ 0x0a, "CTXSW_TIMEOUT" },
|
|
{}
|
|
};
|
|
|
|
static void
|
|
gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
|
|
{
|
|
struct nvkm_device *device = fifo->base.engine.subdev.device;
|
|
struct nvkm_engine *engine;
|
|
struct gf100_fifo_chan *chan;
|
|
u32 engn;
|
|
|
|
for (engn = 0; engn < 6; engn++) {
|
|
u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));
|
|
u32 busy = (stat & 0x80000000);
|
|
u32 save = (stat & 0x00100000); /* maybe? */
|
|
u32 unk0 = (stat & 0x00040000);
|
|
u32 unk1 = (stat & 0x00001000);
|
|
u32 chid = (stat & 0x0000007f);
|
|
(void)save;
|
|
|
|
if (busy && unk0 && unk1) {
|
|
if (!(chan = (void *)fifo->base.channel[chid]))
|
|
continue;
|
|
if (!(engine = gf100_fifo_engine(fifo, engn)))
|
|
continue;
|
|
gf100_fifo_recover(fifo, engine, chan);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_intr_sched(struct gf100_fifo *fifo)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 intr = nvkm_rd32(device, 0x00254c);
|
|
u32 code = intr & 0x000000ff;
|
|
const struct nvkm_enum *en;
|
|
|
|
en = nvkm_enum_find(gf100_fifo_sched_reason, code);
|
|
|
|
nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
|
|
|
|
switch (code) {
|
|
case 0x0a:
|
|
gf100_fifo_intr_sched_ctxsw(fifo);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const struct nvkm_enum
|
|
gf100_fifo_fault_engine[] = {
|
|
{ 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
|
|
{ 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
|
|
{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
|
|
{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
|
|
{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
|
|
{ 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
|
|
{ 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
|
|
{ 0x13, "PCOUNTER" },
|
|
{ 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
|
|
{ 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
|
|
{ 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
|
|
{ 0x17, "PDAEMON" },
|
|
{}
|
|
};
|
|
|
|
static const struct nvkm_enum
|
|
gf100_fifo_fault_reason[] = {
|
|
{ 0x00, "PT_NOT_PRESENT" },
|
|
{ 0x01, "PT_TOO_SHORT" },
|
|
{ 0x02, "PAGE_NOT_PRESENT" },
|
|
{ 0x03, "VM_LIMIT_EXCEEDED" },
|
|
{ 0x04, "NO_CHANNEL" },
|
|
{ 0x05, "PAGE_SYSTEM_ONLY" },
|
|
{ 0x06, "PAGE_READ_ONLY" },
|
|
{ 0x0a, "COMPRESSED_SYSRAM" },
|
|
{ 0x0c, "INVALID_STORAGE_TYPE" },
|
|
{}
|
|
};
|
|
|
|
static const struct nvkm_enum
|
|
gf100_fifo_fault_hubclient[] = {
|
|
{ 0x01, "PCOPY0" },
|
|
{ 0x02, "PCOPY1" },
|
|
{ 0x04, "DISPATCH" },
|
|
{ 0x05, "CTXCTL" },
|
|
{ 0x06, "PFIFO" },
|
|
{ 0x07, "BAR_READ" },
|
|
{ 0x08, "BAR_WRITE" },
|
|
{ 0x0b, "PVP" },
|
|
{ 0x0c, "PMSPPP" },
|
|
{ 0x0d, "PMSVLD" },
|
|
{ 0x11, "PCOUNTER" },
|
|
{ 0x12, "PDAEMON" },
|
|
{ 0x14, "CCACHE" },
|
|
{ 0x15, "CCACHE_POST" },
|
|
{}
|
|
};
|
|
|
|
static const struct nvkm_enum
|
|
gf100_fifo_fault_gpcclient[] = {
|
|
{ 0x01, "TEX" },
|
|
{ 0x0c, "ESETUP" },
|
|
{ 0x0e, "CTXCTL" },
|
|
{ 0x0f, "PROP" },
|
|
{}
|
|
};
|
|
|
|
static void
|
|
gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
|
|
u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
|
|
u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
|
|
u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
|
|
u32 gpc = (stat & 0x1f000000) >> 24;
|
|
u32 client = (stat & 0x00001f00) >> 8;
|
|
u32 write = (stat & 0x00000080);
|
|
u32 hub = (stat & 0x00000040);
|
|
u32 reason = (stat & 0x0000000f);
|
|
struct nvkm_object *engctx = NULL, *object;
|
|
struct nvkm_engine *engine = NULL;
|
|
const struct nvkm_enum *er, *eu, *ec;
|
|
char gpcid[8] = "";
|
|
|
|
er = nvkm_enum_find(gf100_fifo_fault_reason, reason);
|
|
eu = nvkm_enum_find(gf100_fifo_fault_engine, unit);
|
|
if (hub) {
|
|
ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client);
|
|
} else {
|
|
ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client);
|
|
snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
|
|
}
|
|
|
|
if (eu) {
|
|
switch (eu->data2) {
|
|
case NVDEV_SUBDEV_BAR:
|
|
nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
|
|
break;
|
|
case NVDEV_SUBDEV_INSTMEM:
|
|
nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
|
|
break;
|
|
case NVDEV_ENGINE_IFB:
|
|
nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
|
|
break;
|
|
default:
|
|
engine = nvkm_engine(fifo, eu->data2);
|
|
if (engine)
|
|
engctx = nvkm_engctx_get(engine, inst);
|
|
break;
|
|
}
|
|
}
|
|
|
|
nvkm_error(subdev,
|
|
"%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
|
|
"reason %02x [%s] on channel %d [%010llx %s]\n",
|
|
write ? "write" : "read", (u64)vahi << 32 | valo,
|
|
unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "",
|
|
reason, er ? er->name : "", -1, (u64)inst << 12,
|
|
nvkm_client_name(engctx));
|
|
|
|
object = engctx;
|
|
while (object) {
|
|
switch (nv_mclass(object)) {
|
|
case FERMI_CHANNEL_GPFIFO:
|
|
gf100_fifo_recover(fifo, engine, (void *)object);
|
|
break;
|
|
}
|
|
object = object->parent;
|
|
}
|
|
|
|
nvkm_engctx_put(engctx);
|
|
}
|
|
|
|
static const struct nvkm_bitfield
|
|
gf100_fifo_pbdma_intr[] = {
|
|
/* { 0x00008000, "" } seen with null ib push */
|
|
{ 0x00200000, "ILLEGAL_MTHD" },
|
|
{ 0x00800000, "EMPTY_SUBC" },
|
|
{}
|
|
};
|
|
|
|
static void
|
|
gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000));
|
|
u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
|
|
u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
|
|
u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f;
|
|
u32 subc = (addr & 0x00070000) >> 16;
|
|
u32 mthd = (addr & 0x00003ffc);
|
|
u32 show= stat;
|
|
char msg[128];
|
|
|
|
if (stat & 0x00800000) {
|
|
if (!gf100_fifo_swmthd(fifo, chid, mthd, data))
|
|
show &= ~0x00800000;
|
|
}
|
|
|
|
if (show) {
|
|
nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show);
|
|
nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%s] subc %d "
|
|
"mthd %04x data %08x\n",
|
|
unit, show, msg, chid,
|
|
nvkm_client_name_for_fifo_chid(&fifo->base, chid),
|
|
subc, mthd, data);
|
|
}
|
|
|
|
nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
|
|
nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_intr_runlist(struct gf100_fifo *fifo)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 intr = nvkm_rd32(device, 0x002a00);
|
|
|
|
if (intr & 0x10000000) {
|
|
wake_up(&fifo->runlist.wait);
|
|
nvkm_wr32(device, 0x002a00, 0x10000000);
|
|
intr &= ~0x10000000;
|
|
}
|
|
|
|
if (intr) {
|
|
nvkm_error(subdev, "RUNLIST %08x\n", intr);
|
|
nvkm_wr32(device, 0x002a00, intr);
|
|
}
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn)
|
|
{
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04));
|
|
u32 inte = nvkm_rd32(device, 0x002628);
|
|
u32 unkn;
|
|
|
|
nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr);
|
|
|
|
for (unkn = 0; unkn < 8; unkn++) {
|
|
u32 ints = (intr >> (unkn * 0x04)) & inte;
|
|
if (ints & 0x1) {
|
|
nvkm_fifo_uevent(&fifo->base);
|
|
ints &= ~1;
|
|
}
|
|
if (ints) {
|
|
nvkm_error(subdev, "ENGINE %d %d %01x",
|
|
engn, unkn, ints);
|
|
nvkm_mask(device, 0x002628, ints, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_intr_engine(struct gf100_fifo *fifo)
|
|
{
|
|
struct nvkm_device *device = fifo->base.engine.subdev.device;
|
|
u32 mask = nvkm_rd32(device, 0x0025a4);
|
|
while (mask) {
|
|
u32 unit = __ffs(mask);
|
|
gf100_fifo_intr_engine_unit(fifo, unit);
|
|
mask &= ~(1 << unit);
|
|
}
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_intr(struct nvkm_subdev *subdev)
|
|
{
|
|
struct gf100_fifo *fifo = (void *)subdev;
|
|
struct nvkm_device *device = fifo->base.engine.subdev.device;
|
|
u32 mask = nvkm_rd32(device, 0x002140);
|
|
u32 stat = nvkm_rd32(device, 0x002100) & mask;
|
|
|
|
if (stat & 0x00000001) {
|
|
u32 intr = nvkm_rd32(device, 0x00252c);
|
|
nvkm_warn(subdev, "INTR 00000001: %08x\n", intr);
|
|
nvkm_wr32(device, 0x002100, 0x00000001);
|
|
stat &= ~0x00000001;
|
|
}
|
|
|
|
if (stat & 0x00000100) {
|
|
gf100_fifo_intr_sched(fifo);
|
|
nvkm_wr32(device, 0x002100, 0x00000100);
|
|
stat &= ~0x00000100;
|
|
}
|
|
|
|
if (stat & 0x00010000) {
|
|
u32 intr = nvkm_rd32(device, 0x00256c);
|
|
nvkm_warn(subdev, "INTR 00010000: %08x\n", intr);
|
|
nvkm_wr32(device, 0x002100, 0x00010000);
|
|
stat &= ~0x00010000;
|
|
}
|
|
|
|
if (stat & 0x01000000) {
|
|
u32 intr = nvkm_rd32(device, 0x00258c);
|
|
nvkm_warn(subdev, "INTR 01000000: %08x\n", intr);
|
|
nvkm_wr32(device, 0x002100, 0x01000000);
|
|
stat &= ~0x01000000;
|
|
}
|
|
|
|
if (stat & 0x10000000) {
|
|
u32 mask = nvkm_rd32(device, 0x00259c);
|
|
while (mask) {
|
|
u32 unit = __ffs(mask);
|
|
gf100_fifo_intr_fault(fifo, unit);
|
|
nvkm_wr32(device, 0x00259c, (1 << unit));
|
|
mask &= ~(1 << unit);
|
|
}
|
|
stat &= ~0x10000000;
|
|
}
|
|
|
|
if (stat & 0x20000000) {
|
|
u32 mask = nvkm_rd32(device, 0x0025a0);
|
|
while (mask) {
|
|
u32 unit = __ffs(mask);
|
|
gf100_fifo_intr_pbdma(fifo, unit);
|
|
nvkm_wr32(device, 0x0025a0, (1 << unit));
|
|
mask &= ~(1 << unit);
|
|
}
|
|
stat &= ~0x20000000;
|
|
}
|
|
|
|
if (stat & 0x40000000) {
|
|
gf100_fifo_intr_runlist(fifo);
|
|
stat &= ~0x40000000;
|
|
}
|
|
|
|
if (stat & 0x80000000) {
|
|
gf100_fifo_intr_engine(fifo);
|
|
stat &= ~0x80000000;
|
|
}
|
|
|
|
if (stat) {
|
|
nvkm_error(subdev, "INTR %08x\n", stat);
|
|
nvkm_mask(device, 0x002140, stat, 0x00000000);
|
|
nvkm_wr32(device, 0x002100, stat);
|
|
}
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index)
|
|
{
|
|
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
|
|
struct nvkm_device *device = fifo->engine.subdev.device;
|
|
nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
|
|
{
|
|
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
|
|
struct nvkm_device *device = fifo->engine.subdev.device;
|
|
nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
|
|
}
|
|
|
|
static const struct nvkm_event_func
|
|
gf100_fifo_uevent_func = {
|
|
.ctor = nvkm_fifo_uevent_ctor,
|
|
.init = gf100_fifo_uevent_init,
|
|
.fini = gf100_fifo_uevent_fini,
|
|
};
|
|
|
|
static int
|
|
gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|
struct nvkm_oclass *oclass, void *data, u32 size,
|
|
struct nvkm_object **pobject)
|
|
{
|
|
struct gf100_fifo *fifo;
|
|
int ret;
|
|
|
|
ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo);
|
|
*pobject = nv_object(fifo);
|
|
if (ret)
|
|
return ret;
|
|
|
|
INIT_WORK(&fifo->fault, gf100_fifo_recover_work);
|
|
|
|
ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
|
|
&fifo->runlist.mem[0]);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0,
|
|
&fifo->runlist.mem[1]);
|
|
if (ret)
|
|
return ret;
|
|
|
|
init_waitqueue_head(&fifo->runlist.wait);
|
|
|
|
ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0,
|
|
&fifo->user.mem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW,
|
|
&fifo->user.bar);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nv_subdev(fifo)->unit = 0x00000100;
|
|
nv_subdev(fifo)->intr = gf100_fifo_intr;
|
|
nv_engine(fifo)->cclass = &gf100_fifo_cclass;
|
|
nv_engine(fifo)->sclass = gf100_fifo_sclass;
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
gf100_fifo_dtor(struct nvkm_object *object)
|
|
{
|
|
struct gf100_fifo *fifo = (void *)object;
|
|
|
|
nvkm_gpuobj_unmap(&fifo->user.bar);
|
|
nvkm_gpuobj_ref(NULL, &fifo->user.mem);
|
|
nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]);
|
|
nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]);
|
|
|
|
nvkm_fifo_destroy(&fifo->base);
|
|
}
|
|
|
|
static int
|
|
gf100_fifo_init(struct nvkm_object *object)
|
|
{
|
|
struct gf100_fifo *fifo = (void *)object;
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
int ret, i;
|
|
|
|
ret = nvkm_fifo_init(&fifo->base);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nvkm_wr32(device, 0x000204, 0xffffffff);
|
|
nvkm_wr32(device, 0x002204, 0xffffffff);
|
|
|
|
fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204));
|
|
nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr);
|
|
|
|
/* assign engines to PBDMAs */
|
|
if (fifo->spoon_nr >= 3) {
|
|
nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */
|
|
nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */
|
|
nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */
|
|
nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */
|
|
nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */
|
|
nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */
|
|
}
|
|
|
|
/* PBDMA[n] */
|
|
for (i = 0; i < fifo->spoon_nr; i++) {
|
|
nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
|
|
nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
|
|
nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
|
|
}
|
|
|
|
nvkm_mask(device, 0x002200, 0x00000001, 0x00000001);
|
|
nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
|
|
|
|
nvkm_wr32(device, 0x002100, 0xffffffff);
|
|
nvkm_wr32(device, 0x002140, 0x7fffffff);
|
|
nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
|
|
return 0;
|
|
}
|
|
|
|
struct nvkm_oclass *
|
|
gf100_fifo_oclass = &(struct nvkm_oclass) {
|
|
.handle = NV_ENGINE(FIFO, 0xc0),
|
|
.ofuncs = &(struct nvkm_ofuncs) {
|
|
.ctor = gf100_fifo_ctor,
|
|
.dtor = gf100_fifo_dtor,
|
|
.init = gf100_fifo_init,
|
|
.fini = _nvkm_fifo_fini,
|
|
},
|
|
};
|